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version: 14.3.0-7 (UNRELEASED)
commit: 39ea76304d57617bd92674237f1fc91c5c12ccd5
This commit is contained in:
Konstantin Demin
2025-09-07 18:09:24 +03:00
parent 08abd3e546
commit e7e0fc078c
14 changed files with 2804 additions and 50 deletions
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40
debian/patches/gcc-distro-specs.diff vendored
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@@ -14,7 +14,7 @@
#define INCLUDE_STRING
#include "config.h"
#include "system.h"
@@ -988,6 +993,113 @@ proper position among the other output f
@@ -988,6 +993,127 @@ proper position among the other output f
#define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L %G}"
#endif
@@ -106,8 +106,22 @@
+# endif
+#endif
+
+/* Enable sframe support by default. */
+#ifndef SFRAME_SPEC
+# ifdef DIST_DEFAULT_SFRAME
+# define SFRAME_SPEC " %{!m16:%{!m32:%{!mx32:%{!ffreestanding:--gsframe}}}}"
+# else
+# define SFRAME_SPEC ""
+# endif
+#endif
+
+/* Don't enable any of those for the offload compilers,
+ unsupported. */
+#if !defined(DISTRO_DEFAULT_ASM_SPEC) && !defined(ACCEL_COMPILER)
+# define DISTRO_DEFAULT_ASM_SPEC SFRAME_SPEC
+#else
+# define DISTRO_DEFAULT_ASM_SPEC ""
+#endif
+#if !defined(DISTRO_DEFAULT_CPP_SPEC) && !defined(ACCEL_COMPILER)
+# define DISTRO_DEFAULT_CPP_SPEC TIMET64_SPEC FORTIFY_SOURCE_SPEC
+#else
@@ -128,7 +142,7 @@
#ifndef LINK_SSP_SPEC
#ifdef TARGET_LIBC_PROVIDES_SSP
#define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \
@@ -1044,7 +1156,7 @@ proper position among the other output f
@@ -1044,7 +1170,7 @@ proper position among the other output f
#ifndef LINK_PIE_SPEC
#ifdef HAVE_LD_PIE
#ifndef LD_PIE_SPEC
@@ -137,7 +151,7 @@
#endif
#else
#define LD_PIE_SPEC ""
@@ -1161,6 +1273,7 @@ proper position among the other output f
@@ -1161,6 +1287,7 @@ proper position among the other output f
"%{flto|flto=*:%<fcompare-debug*} \
%{flto} %{fno-lto} %{flto=*} %l " LINK_PIE_SPEC \
"%{fuse-ld=*:-fuse-ld=%*} " LINK_COMPRESS_DEBUG_SPEC \
@@ -145,16 +159,17 @@
"%X %{o*} %{e*} %{N} %{n} %{r}\
%{s} %{t} %{u*} %{z} %{Z} %{!nostdlib:%{!r:%{!nostartfiles:%S}}} \
%{static|no-pie|static-pie:} %@{L*} %(link_libgcc) " \
@@ -1205,6 +1318,8 @@ static const char *cpp_spec = CPP_SPEC;
@@ -1205,6 +1332,9 @@ static const char *cpp_spec = CPP_SPEC;
static const char *cc1_spec = CC1_SPEC OS_CC1_SPEC;
static const char *cc1plus_spec = CC1PLUS_SPEC;
static const char *link_gcc_c_sequence_spec = LINK_GCC_C_SEQUENCE_SPEC;
+static const char *distro_default_asm_spec = DISTRO_DEFAULT_ASM_SPEC;
+static const char *distro_default_cpp_spec = DISTRO_DEFAULT_CPP_SPEC;
+static const char *distro_default_spec = DISTRO_DEFAULT_SPEC;
static const char *link_ssp_spec = LINK_SSP_SPEC;
static const char *asm_spec = ASM_SPEC;
static const char *asm_final_spec = ASM_FINAL_SPEC;
@@ -1265,7 +1380,7 @@ static const char *cpp_options =
@@ -1265,7 +1395,7 @@ static const char *cpp_options =
"%(cpp_unique_options) %1 %{m*} %{std*&ansi&trigraphs} %{W*&pedantic*} %{w}\
%{f*} %{g*:%{%:debug-level-gt(0):%{g*}\
%{!fno-working-directory:-fworking-directory}}} %{O*}\
@@ -163,7 +178,15 @@
/* Pass -d* flags, possibly modifying -dumpdir, -dumpbase et al.
@@ -1459,9 +1574,9 @@ static const struct compiler default_com
@@ -1303,6 +1433,7 @@ static const char *asm_options =
to the assembler equivalents. */
"%{v} %{w:-W} %{I*} "
#endif
+DISTRO_DEFAULT_ASM_SPEC
"%(asm_debug_option)"
ASM_COMPRESS_DEBUG_SPEC
"%a %Y %{c:%W{o*}%{!o*:-o %w%b%O}}%{!c:-o %d%w%u%O}";
@@ -1459,9 +1590,9 @@ static const struct compiler default_com
%{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \
%(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\
cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \
@@ -175,7 +198,7 @@
%{!fsyntax-only:%(invoke_as)}}}}", 0, 0, 1},
{"-",
"%{!E:%e-E or -x required when input is from standard input}\
@@ -1475,18 +1590,18 @@ static const struct compiler default_com
@@ -1475,18 +1606,18 @@ static const struct compiler default_com
%{save-temps*|traditional-cpp|no-integrated-cpp:%(trad_capable_cpp) \
%(cpp_options) -o %{save-temps*:%b.i} %{!save-temps*:%g.i} \n\
cc1 -fpreprocessed %{save-temps*:%b.i} %{!save-temps*:%g.i} \
@@ -197,11 +220,12 @@
{".s", "@assembler", 0, 0, 0},
{"@assembler",
"%{!M:%{!MM:%{!E:%{!S:as %(asm_debug) %(asm_options) %i %A }}}}", 0, 0, 0},
@@ -1718,6 +1833,8 @@ static struct spec_list static_specs[] =
@@ -1718,6 +1849,9 @@ static struct spec_list static_specs[] =
INIT_STATIC_SPEC ("cc1_options", &cc1_options),
INIT_STATIC_SPEC ("cc1plus", &cc1plus_spec),
INIT_STATIC_SPEC ("link_gcc_c_sequence", &link_gcc_c_sequence_spec),
+ INIT_STATIC_SPEC ("distro_defaults", &distro_default_spec),
+ INIT_STATIC_SPEC ("distro_defaults_asm", &distro_default_asm_spec),
+ INIT_STATIC_SPEC ("distro_defaults_cpp", &distro_default_cpp_spec),
INIT_STATIC_SPEC ("link_ssp", &link_ssp_spec),
INIT_STATIC_SPEC ("endfile", &endfile_spec),

16
debian/patches/git-doc-updates.diff vendored
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@@ -1,7 +1,7 @@
# DP: updates from the 14 branch upto 20250810 (documentation).
# DP: updates from the 14 branch upto 20250829 (documentation).
LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \
c9cd41fba9ebd288c4f101e4b99da934bcb96a11 959349ffd61a27c7d881374b682389a8d9d78a9d \
c9cd41fba9ebd288c4f101e4b99da934bcb96a11 591d04b6db957715fd88e9ebf5be4d96a5bc2caa \
| awk '/^diff .*\.texi/ {skip=0; print; next} /^diff / {skip=1; next} skip==0' \
| grep -v -E '^(diff|index)'
@@ -93,3 +93,15 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \
@item knl
Intel Knights Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
--- a/src/gcc/doc/sourcebuild.texi
+++ b/src/gcc/doc/sourcebuild.texi
@@ -2346,6 +2346,9 @@ whether it does so by default).
@itemx aarch64_sve1024_hw
@itemx aarch64_sve2048_hw
Like @code{aarch64_sve_hw}, but also test for an exact hardware vector length.
+@item aarch64_sme_hw
+AArch64 target that is able to generate and execute SME code (regardless of
+whether it does so by default).
@item aarch64_fjcvtzs_hw
AArch64 target that is able to generate and execute armv8.3-a FJCVTZS

2300
debian/patches/git-updates.diff vendored
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File diff suppressed because it is too large Load Diff

20
debian/patches/libphobos-ppc64el.diff vendored Normal file
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@@ -0,0 +1,20 @@
# DP: build libphobos on ppc64el when configured --with-long-double-format=ieee
--- a/src/libphobos/configure.tgt
+++ b/src/libphobos/configure.tgt
@@ -48,6 +48,15 @@
power*-*-freebsd*)
LIBPHOBOS_SUPPORTED=yes
;;
+ powerpc64le-*-linux*)
+ LIBPHOBOS_SUPPORTED=yes
+ case "$ac_configure_args" in
+ *--with-long-double-format=ieee*)
+ ;;
+ *)
+ LIBDRUNTIME_ONLY=yes
+ esac
+ ;;
power*-*-linux*)
LIBPHOBOS_SUPPORTED=yes
LIBDRUNTIME_ONLY=yes

12
debian/patches/libphobos-sparc64.diff vendored Normal file
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@@ -0,0 +1,12 @@
--- a/src/libphobos/configure.tgt
+++ b/src/libphobos/configure.tgt
@@ -61,6 +61,9 @@ case "${target}" in
s390*-linux*)
LIBPHOBOS_SUPPORTED=yes
;;
+ sparc64-*-linux*)
+ LIBPHOBOS_SUPPORTED=yes
+ ;;
x86_64-*-freebsd* | i?86-*-freebsd*)
LIBPHOBOS_SUPPORTED=yes
;;

23
debian/patches/newlib-p2.diff vendored Normal file
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@@ -0,0 +1,23 @@
commit f13e8e21599ff12ea76980d6a8b19b0a5ebe9bed
Author: Andrew Stubbs <ams@baylibre.com>
Date: Thu Aug 7 13:09:41 2025 +0000
amdgcn, libm: fix infinite loop
--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c
@@ -70,8 +70,11 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y)
v64si iy;
VECTOR_IF (hy < 0x00800000, cond) // subnormal y
iy = VECTOR_INIT (-126);
- for (v64si i = (hy << 8); !ALL_ZEROES_P (cond & (i >= 0)); i <<= 1)
- VECTOR_COND_MOVE (iy, iy - 1, cond & (i >= 0));
+ for (v64si i = (hy << 8); !ALL_ZEROES_P (cond & (i >= 0)); /* i <<= 1 */)
+ {
+ VECTOR_COND_MOVE (iy, iy - 1, cond & (i >= 0));
+ VECTOR_COND_MOVE (i, i << 1, cond & (i >= 0));
+ }
VECTOR_ELSE (cond)
VECTOR_COND_MOVE (iy, (hy >> 23) - 127, cond);
VECTOR_ENDIF

301
debian/patches/newlib-p3.diff vendored Normal file
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@@ -0,0 +1,301 @@
commit bd409f3c12e28e1464dec7fd0d45db30280f1e56
Author: Andrew Stubbs <ams@baylibre.com>
Date: Wed Aug 27 10:11:25 2025 +0000
amdgcn, libm: fix vector ilogb bugs (bug 33272)
--- a/newlib/libm/machine/amdgcn/amdgcn_veclib.h
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/amdgcn_veclib.h
@@ -267,7 +267,15 @@ do { \
__tmp; \
})
-#define VECTOR_WHILE(cond, cond_var, prev_cond_var) \
+#define VECTOR_WHILE(cond, cond_var) \
+{ \
+ __auto_type cond_var = __mask; \
+ for (;;) { \
+ cond_var &= __builtin_convertvector (cond, __typeof (cond_var)); \
+ if (ALL_ZEROES_P (cond_var)) \
+ break;
+
+#define VECTOR_WHILE2(cond, cond_var, prev_cond_var) \
{ \
__auto_type cond_var = prev_cond_var; \
for (;;) { \
--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_fmod.c
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_fmod.c
@@ -61,17 +61,19 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y)
v64si ix;
VECTOR_IF (hx < 0x00100000, cond) // subnormal x
VECTOR_IF2 (hx == 0, cond2, cond)
- ix = VECTOR_INIT (-1043);
- for (v64si i = __builtin_convertvector (lx, v64si);
- !ALL_ZEROES_P (cond2 & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0));
+ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1043), cond2);
+ v64si i = __builtin_convertvector (lx, v64si);
+ VECTOR_WHILE2 (i > 0, cond3, cond2);
+ VECTOR_COND_MOVE (ix, ix - 1, cond3);
+ VECTOR_COND_MOVE (i, i << 1, cond3);
+ VECTOR_ENDWHILE
VECTOR_ELSE2 (cond2, cond)
- ix = VECTOR_INIT (-1022);
- for (v64si i = __builtin_convertvector (hx << 11, v64si);
- !ALL_ZEROES_P (cond2 & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0));
+ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1022), cond2);
+ v64si i = __builtin_convertvector (hx << 11, v64si);
+ VECTOR_WHILE2 (i > 0, cond3, cond2)
+ VECTOR_COND_MOVE (ix, ix - 1, cond3);
+ VECTOR_COND_MOVE (i, i << 1, cond3);
+ VECTOR_ENDWHILE
VECTOR_ENDIF
VECTOR_ELSE (cond)
VECTOR_COND_MOVE (ix, (hx >> 20) - 1023, cond);
@@ -81,17 +83,19 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y)
v64si iy;
VECTOR_IF (hy < 0x00100000, cond) // subnormal y
VECTOR_IF2 (hy == 0, cond2, cond)
- iy = VECTOR_INIT (-1043);
- for (v64si i = __builtin_convertvector (ly, v64si);
- !ALL_ZEROES_P (cond2 & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (iy, iy - 1, cond2 & (i > 0));
+ VECTOR_COND_MOVE (iy, VECTOR_INIT (-1043), cond2);
+ v64si i = __builtin_convertvector (ly, v64si);
+ VECTOR_WHILE2 (i > 0, cond3, cond2);
+ VECTOR_COND_MOVE (iy, iy - 1, cond3);
+ VECTOR_COND_MOVE (i, i << 1, cond3);
+ VECTOR_ENDWHILE
VECTOR_ELSE2 (cond2, cond)
- iy = VECTOR_INIT (-1022);
- for (v64si i = __builtin_convertvector (hy << 11, v64si);
- !ALL_ZEROES_P (cond2 & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (iy, iy - 1, cond2 & (i > 0));
+ VECTOR_COND_MOVE (iy, VECTOR_INIT (-1022), cond2);
+ v64si i = __builtin_convertvector (hy << 11, v64si);
+ VECTOR_WHILE2 (i > 0, cond3, cond2);
+ VECTOR_COND_MOVE (iy, iy - 1, cond3);
+ VECTOR_COND_MOVE (i, i << 1, cond3);
+ VECTOR_ENDWHILE
VECTOR_ENDIF
VECTOR_ELSE (cond)
VECTOR_COND_MOVE (iy, (hy >> 20) - 1023, cond);
@@ -130,29 +134,26 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y)
/* fix point fmod */
v64si n = ix - iy;
- v64si cond = n != 0;
- while (!ALL_ZEROES_P (cond))
- {
- hz = hx - hy;
- lz = lx - ly;
- VECTOR_IF2 (lx < ly, cond2, cond)
- VECTOR_COND_MOVE (hz, hz - 1, cond2);
- VECTOR_ENDIF
- VECTOR_IF2 (hz < 0, cond2, cond)
- VECTOR_COND_MOVE (hx, hx + hx + (__builtin_convertvector(lx, v64usi) >> 31), cond2);
- VECTOR_COND_MOVE (lx, lx + lx, cond2);
- VECTOR_ELSE2 (cond2, cond)
- VECTOR_IF2 ((hz | lz) == 0, cond3, cond2) // return sign(x)*0
- VECTOR_RETURN (zeroes, cond3);
- VECTOR_ENDIF
- VECTOR_COND_MOVE (hx, hz + hz + (__builtin_convertvector(lz, v64usi) >> 31), cond2);
- VECTOR_COND_MOVE (lx, lz + lz, cond2);
+ VECTOR_WHILE (n != 0, cond)
+ hz = hx - hy;
+ lz = lx - ly;
+ VECTOR_IF2 (lx < ly, cond2, cond)
+ VECTOR_COND_MOVE (hz, hz - 1, cond2);
+ VECTOR_ENDIF
+ VECTOR_IF2 (hz < 0, cond2, cond)
+ VECTOR_COND_MOVE (hx, hx + hx + (__builtin_convertvector(lx, v64usi) >> 31), cond2);
+ VECTOR_COND_MOVE (lx, lx + lx, cond2);
+ VECTOR_ELSE2 (cond2, cond)
+ VECTOR_IF2 ((hz | lz) == 0, cond3, cond2) // return sign(x)*0
+ VECTOR_RETURN (zeroes, cond3);
VECTOR_ENDIF
+ VECTOR_COND_MOVE (hx, hz + hz + (__builtin_convertvector(lz, v64usi) >> 31), cond2);
+ VECTOR_COND_MOVE (lx, lz + lz, cond2);
+ VECTOR_ENDIF
- n += cond; // Active lanes should be -1
- cond &= (n != 0);
- }
+ VECTOR_COND_MOVE (n, n - 1, cond);
+ VECTOR_ENDWHILE
hz = hx - hy;
lz = lx - ly;
@@ -164,15 +165,11 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y)
/* convert back to floating value and restore the sign */
VECTOR_RETURN (zeroes, (hx | lx) == 0); // return sign(x)*0
- cond = hx < 0x00100000;
- while (!ALL_ZEROES_P (cond)) // normalize x
- {
- VECTOR_COND_MOVE (hx, hx + hx + (lx >> 31), cond);
- VECTOR_COND_MOVE (lx, lx + lx, cond);
- iy += cond; // Active lanes should be -1
-
- cond &= (hx < 0x00100000);
- }
+ VECTOR_WHILE (hx < 0x00100000, cond) // normalize x
+ VECTOR_COND_MOVE (hx, hx + hx + (lx >> 31), cond);
+ VECTOR_COND_MOVE (lx, lx + lx, cond);
+ VECTOR_COND_MOVE (iy, iy - 1, cond);
+ VECTOR_ENDWHILE
VECTOR_IF (iy >= -1022, cond) // normalize output
VECTOR_COND_MOVE (hx, (hx - 0x00100000) | ((iy + 1023) << 20), cond);
INSERT_WORDS (x, hx | sx, lx, cond);
--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_ilogb.c
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_ilogb.c
@@ -36,17 +36,19 @@ DEF_VD_MATH_PRED (v64si, ilogb, v64df x)
VECTOR_IF (hx < 0x00100000, cond)
VECTOR_RETURN (VECTOR_INIT (-__INT_MAX__), cond & ((hx | lx) == 0)); // FP_ILOGB0
VECTOR_IF2 (hx == 0, cond2, cond)
- ix = VECTOR_INIT (-1043);
- for (v64si i = lx;
- !ALL_ZEROES_P (cond2 & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0));
+ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1043), cond2);
+ v64si i = lx;
+ VECTOR_WHILE2 (i > 0, cond3, cond2)
+ VECTOR_COND_MOVE (ix, ix - 1, cond3);
+ VECTOR_COND_MOVE (i, i << 1, cond3);
+ VECTOR_ENDWHILE
VECTOR_ELSE2 (cond2, cond)
- ix = VECTOR_INIT (-1022);
- for (v64si i = (hx << 11);
- !ALL_ZEROES_P (cond2 & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0));
+ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1022), cond2);
+ v64si i = (hx << 11);
+ VECTOR_WHILE2 (i > 0, cond3, cond2)
+ VECTOR_COND_MOVE (ix, ix - 1, cond3);
+ VECTOR_COND_MOVE (i, i << 1, cond3);
+ VECTOR_ENDWHILE
VECTOR_ENDIF
VECTOR_RETURN (ix, cond);
VECTOR_ENDIF
--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c
@@ -57,11 +57,12 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y)
/* determine ix = ilogb(x) */
v64si ix;
VECTOR_IF (hx < 0x00800000, cond) // subnormal x
- ix = VECTOR_INIT (-126);
- for (v64si i = (hx << 8);
- !ALL_ZEROES_P (cond & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (ix, ix - 1, cond & (i > 0));
+ VECTOR_COND_MOVE (ix, VECTOR_INIT (-126), cond);
+ v64si i = hx << 8;
+ VECTOR_WHILE2 (i > 0, cond2, cond)
+ VECTOR_COND_MOVE (ix, ix - 1, cond2);
+ VECTOR_COND_MOVE (i, i << 1, cond2);
+ VECTOR_ENDWHILE
VECTOR_ELSE (cond)
VECTOR_COND_MOVE (ix, (hx >> 23) - 127, cond);
VECTOR_ENDIF
@@ -69,12 +70,12 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y)
/* determine iy = ilogb(y) */
v64si iy;
VECTOR_IF (hy < 0x00800000, cond) // subnormal y
- iy = VECTOR_INIT (-126);
- for (v64si i = (hy << 8); !ALL_ZEROES_P (cond & (i >= 0)); /* i <<= 1 */)
- {
- VECTOR_COND_MOVE (iy, iy - 1, cond & (i >= 0));
- VECTOR_COND_MOVE (i, i << 1, cond & (i >= 0));
- }
+ VECTOR_COND_MOVE (iy, VECTOR_INIT (-126), cond);
+ v64si i = (hy << 8);
+ VECTOR_WHILE2 (i >= 0, cond2, cond)
+ VECTOR_COND_MOVE (iy, iy - 1, cond2);
+ VECTOR_COND_MOVE (i, i << 1, cond2);
+ VECTOR_ENDWHILE
VECTOR_ELSE (cond)
VECTOR_COND_MOVE (iy, (hy >> 23) - 127, cond);
VECTOR_ENDIF
@@ -99,24 +100,21 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y)
/* fix point fmod */
v64si n = ix - iy;
- v64si cond = n != 0;
- while (!ALL_ZEROES_P (cond))
- {
- hz = hx - hy;
- VECTOR_IF2 (hz < 0, cond2, cond)
- VECTOR_COND_MOVE (hx, hx + hx, cond2);
- VECTOR_ELSE2 (cond2, cond)
- VECTOR_IF2 (hz == 0, cond3, cond2) // return sign(x)*0
- VECTOR_RETURN (zeroes, cond3);
- VECTOR_ELSE2 (cond3, cond2)
- VECTOR_COND_MOVE (hx, hz + hz, cond2);
- VECTOR_ENDIF
+ VECTOR_WHILE (n != 0, cond)
+ hz = hx - hy;
+ VECTOR_IF2 (hz < 0, cond2, cond)
+ VECTOR_COND_MOVE (hx, hx + hx, cond2);
+ VECTOR_ELSE2 (cond2, cond)
+ VECTOR_IF2 (hz == 0, cond3, cond2) // return sign(x)*0
+ VECTOR_RETURN (zeroes, cond3);
+ VECTOR_ELSE2 (cond3, cond2)
+ VECTOR_COND_MOVE (hx, hz + hz, cond2);
VECTOR_ENDIF
+ VECTOR_ENDIF
- n += cond; // Active lanes should be -1
- cond &= (n != 0);
- }
+ n += cond; // Active lanes should be -1
+ VECTOR_ENDWHILE
hz = hx - hy;
VECTOR_COND_MOVE (hx, hz, hz >= 0);
@@ -124,14 +122,10 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y)
/* convert back to floating value and restore the sign */
VECTOR_RETURN (zeroes, hx == 0); // return sign(x)*0
- cond = hx < 0x00800000;
- while (!ALL_ZEROES_P (cond)) // normalize x
- {
+ VECTOR_WHILE (hx < 0x00800000, cond) // normalize x
VECTOR_COND_MOVE (hx, hx + hx, cond);
iy += cond; // Active lanes should be -1
-
- cond &= (hx < 0x00800000);
- }
+ VECTOR_ENDWHILE
VECTOR_IF (iy >= -126, cond) // normalize output
VECTOR_COND_MOVE (hx, (hx - 0x00800000) | ((iy + 127) << 23), cond);
SET_FLOAT_WORD (x, hx | sx, cond);
--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_ilogb.c
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_ilogb.c
@@ -38,11 +38,12 @@ DEF_VS_MATH_FUNC (v64si, ilogbf, v64sf x)
VECTOR_RETURN (VECTOR_INIT (-__INT_MAX__), cond); // FP_ILOGB0
VECTOR_ENDIF
VECTOR_IF (FLT_UWORD_IS_SUBNORMAL (hx), cond)
- ix = VECTOR_INIT (-126);
- for (v64si i = (hx << 8);
- !ALL_ZEROES_P (cond & (i > 0));
- i <<= 1)
- VECTOR_COND_MOVE (ix, ix - 1, cond & (i > 0));
+ VECTOR_COND_MOVE (ix, VECTOR_INIT (-126), cond);
+ v64si i = (hx << 8);
+ VECTOR_WHILE2 (i > 0, cond2, cond)
+ VECTOR_COND_MOVE (ix, ix - 1, cond2);
+ VECTOR_COND_MOVE (i, i << 1, cond2);
+ VECTOR_ENDWHILE
VECTOR_RETURN (ix, cond);
VECTOR_ELSEIF (~FLT_UWORD_IS_FINITE (hx), cond)
VECTOR_RETURN (VECTOR_INIT (__INT_MAX__), cond);

43
debian/patches/newlib-pr119325.diff vendored Normal file
View File

@@ -0,0 +1,43 @@
From 2ef1a37e7823b21eda524972c006e0e8c26f97b3 Mon Sep 17 00:00:00 2001
From: Andrew Stubbs <ams@baylibre.com>
Date: Thu, 20 Mar 2025 09:32:31 +0000
Subject: [PATCH] Fix GCN SIMD libm bug
Since January, GCC has been miscompiling Newlib libm on AMD GCN due to
undefined behaviour in the RESIZE_VECTOR macro. It was "working" but expanding
the size of a vector would no longer zero the additional lanes, as it expected.
See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119325
---
newlib/libm/machine/amdgcn/amdgcn_veclib.h | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/amdgcn_veclib.h
+++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/amdgcn_veclib.h
@@ -85,8 +85,21 @@ typedef union {
#define RESIZE_VECTOR(to_t, from) \
({ \
- __auto_type __from = (from); \
- *((to_t *) &__from); \
+ to_t __to; \
+ if (VECTOR_WIDTH (to_t) < VECTOR_WIDTH (__typeof (from))) \
+ asm ("; no-op cast %0" : "=v"(__to) : "0"(from)); \
+ else \
+ { \
+ unsigned long __mask = -1L; \
+ int lanes = VECTOR_WIDTH (__typeof (from)); \
+ __mask <<= lanes; \
+ __builtin_choose_expr ( \
+ V_SF_SI_P (to_t), \
+ ({asm ("v_mov_b32 %0, 0" : "=v"(__to) : "0"(from), "e"(__mask));}), \
+ ({asm ("v_mov_b32 %H0, 0\n\t" \
+ "v_mov_b32 %L0, 0" : "=v"(__to) : "0"(from), "e"(__mask));})); \
+ } \
+ __to; \
})
/* Bit-wise cast vector FROM to type TO_T. */
--
2.43.5