diff --git a/debian/control b/debian/control index 6ecc928..23d2e69 100644 --- a/debian/control +++ b/debian/control @@ -14,11 +14,11 @@ Build-Depends: debhelper (>= 11), dpkg-dev (>= 1.17.14), g++-multilib [amd64 i38 gperf, bison, flex, gettext, nvptx-tools [amd64 arm64 ppc64el], amdgcn-tools-19 [amd64], texinfo, locales-all, sharutils, - procps, gnat-14:native [!arc !ia64 !sh3 !sh3eb !sh4eb !m68k], g++-14:native [!m68k], gnat-13:native [m68k], g++-13:native [m68k], netbase, gdc-14:native [!alpha !arc !ia64 !m68k !sh4 !s390 !sparc64 !hurd-amd64 !hurd-i386], python3:any, cargo [!alpha !hppa !ia64 !m68k !sh4 !x32], + procps, gnat-13:native [!arc !ia64 !sh3 !sh3eb !sh4eb], g++-13:native, netbase, gdc-13:native [!alpha !arc !ia64 !m68k !sh4 !s390 !hurd-amd64 !hurd-i386], python3:any, cargo [!alpha !hppa !ia64 !m68k !sh4 !x32], libisl-dev (>= 0.20), libmpc-dev (>= 1.0), libmpfr-dev (>= 3.0.0-9~), libgmp-dev (>= 2:5.0.1~), lib32z1-dev [amd64], lib64z1-dev [i386], unzip , dejagnu [!alpha !riscv64 !hurd-amd64 !hurd-i386] , git [!alpha !riscv64 !hurd-amd64 !hurd-i386] , coreutils, chrpath, lsb-release, quilt, time, pkgconf, libgc-dev, - g++-14-for-host , gobjc-14-for-host [!avr] , gfortran-14-for-host , gdc-14-for-host [!alpha !arc !ia64 !m68k !sh4 !s390 !sparc64 !hurd-amd64 !hurd-i386] , gccgo-14-for-host [!arc !avr !hppa !loong64 !m68k !sh4] , gnat-14-for-host [!arc !ia64 !sh3 !sh3eb !sh4eb] , gm2-14-for-host [!powerpc !ppc64 !sh4] , + g++-14-for-host , gobjc-14-for-host [!avr] , gfortran-14-for-host , gdc-14-for-host [!alpha !arc !ia64 !m68k !sh4 !s390 !hurd-amd64 !hurd-i386] , gccgo-14-for-host [!arc !avr !hppa !loong64 !m68k !sh4] , gnat-14-for-host [!arc !ia64 !sh3 !sh3eb !sh4eb] , gm2-14-for-host [!powerpc !ppc64 !sh4] , Build-Depends-Indep: doxygen , graphviz , ghostscript , texlive-latex-base , xsltproc , libxml2-utils , docbook-xsl-ns , Homepage: http://gcc.gnu.org/ Vcs-Browser: https://git.krd.sh/trixie-backports/gcc-14 @@ -4432,6 +4432,17 @@ Description: GNU D compiler (version 2) for the sparc-linux-gnu architecture . This compiler supports D language version 2. +Package: gdc-14-sparc64-linux-gnu +Architecture: sparc64 +Multi-Arch: foreign +Depends: gcc-14-base (>= ${gcc:SoftVersion}), g++-14-sparc64-linux-gnu (>= ${gcc:Version}), ${dep:gdccross}, ${dep:phobosdev}, ${shlibs:Depends}, ${misc:Depends} +Description: GNU D compiler (version 2) for the sparc64-linux-gnu architecture + This is the GNU D compiler for the sparc64-linux-gnu architecture, + which compiles D on platforms supported by gcc. + It uses the gcc backend to generate optimised code. + . + This compiler supports D language version 2. + Package: gdc-14-s390x-linux-gnu Architecture: s390x Multi-Arch: foreign @@ -4585,7 +4596,7 @@ Description: GNU D compiler (version 2, multilib support) Package: libgphobos-14-dev X-DH-Build-For-Type: target -Architecture: amd64 arm64 armel armhf i386 x32 hppa mips mips64 mipsel mips64el mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el mips64r6 mips64r6el riscv64 s390x loong64 powerpc ppc64 ppc64el +Architecture: amd64 arm64 armel armhf hppa i386 loong64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 ppc64el riscv64 s390x sparc64 x32 Multi-Arch: same Section: libdevel Depends: gcc-14-base (= ${gcc:Version}), libgphobos5 (>= ${gdc:Version}), @@ -4645,7 +4656,7 @@ Description: Phobos D standard library (x32 development files) Package: libgphobos5 X-DH-Build-For-Type: target Section: libs -Architecture: amd64 arm64 armel armhf i386 x32 hppa mips mips64 mipsel mips64el mipsn32 mipsn32el mipsr6 mipsr6el mipsn32r6 mipsn32r6el mips64r6 mips64r6el riscv64 s390x loong64 powerpc ppc64 ppc64el +Architecture: amd64 arm64 armel armhf hppa i386 loong64 mips mips64 mips64el mips64r6 mips64r6el mipsel mipsn32 mipsn32el mipsn32r6 mipsn32r6el mipsr6 mipsr6el powerpc ppc64 ppc64el riscv64 s390x sparc64 x32 Multi-Arch: same Depends: gcc-14-base (= ${gcc:Version}), ${shlibs:Depends}, ${misc:Depends} Description: Phobos D standard library (runtime library) diff --git a/debian/patches/gcc-distro-specs.diff b/debian/patches/gcc-distro-specs.diff index a9b1f8a..a8d6ba3 100644 --- a/debian/patches/gcc-distro-specs.diff +++ b/debian/patches/gcc-distro-specs.diff @@ -14,7 +14,7 @@ #define INCLUDE_STRING #include "config.h" #include "system.h" -@@ -988,6 +993,113 @@ proper position among the other output f +@@ -988,6 +993,127 @@ proper position among the other output f #define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L %G}" #endif @@ -106,8 +106,22 @@ +# endif +#endif + ++/* Enable sframe support by default. */ ++#ifndef SFRAME_SPEC ++# ifdef DIST_DEFAULT_SFRAME ++# define SFRAME_SPEC " %{!m16:%{!m32:%{!mx32:%{!ffreestanding:--gsframe}}}}" ++# else ++# define SFRAME_SPEC "" ++# endif ++#endif ++ +/* Don't enable any of those for the offload compilers, + unsupported. */ ++#if !defined(DISTRO_DEFAULT_ASM_SPEC) && !defined(ACCEL_COMPILER) ++# define DISTRO_DEFAULT_ASM_SPEC SFRAME_SPEC ++#else ++# define DISTRO_DEFAULT_ASM_SPEC "" ++#endif +#if !defined(DISTRO_DEFAULT_CPP_SPEC) && !defined(ACCEL_COMPILER) +# define DISTRO_DEFAULT_CPP_SPEC TIMET64_SPEC FORTIFY_SOURCE_SPEC +#else @@ -128,7 +142,7 @@ #ifndef LINK_SSP_SPEC #ifdef TARGET_LIBC_PROVIDES_SSP #define LINK_SSP_SPEC "%{fstack-protector|fstack-protector-all" \ -@@ -1044,7 +1156,7 @@ proper position among the other output f +@@ -1044,7 +1170,7 @@ proper position among the other output f #ifndef LINK_PIE_SPEC #ifdef HAVE_LD_PIE #ifndef LD_PIE_SPEC @@ -137,7 +151,7 @@ #endif #else #define LD_PIE_SPEC "" -@@ -1161,6 +1273,7 @@ proper position among the other output f +@@ -1161,6 +1287,7 @@ proper position among the other output f "%{flto|flto=*:% ++ ++ Backported from master: ++ 2025-07-23 Martin Jambor ++ ++ PR tree-optimization/119085 ++ * tree-sra.cc (sort_and_splice_var_accesses): Prevent total ++ scalarization if two incompatible aggregates access the same place. ++ ++2025-08-20 Martin Jambor ++ ++ Backported from master: ++ 2025-07-18 Martin Jambor ++ ++ PR tree-optimization/117423 ++ * tree-sra.cc (analyze_access_subtree): Fix computation of grp_covered ++ flag. ++ ++2025-08-20 Georg-Johann Lay ++ ++ Backported from master: ++ 2025-08-20 Georg-Johann Lay ++ ++ PR target/121608 ++ * config/avr/specs.h (LINK_RELAX_SPEC): Wrap in %{!r...}. ++ ++2025-08-18 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-18 Richard Sandiford ++ ++ PR target/121118 ++ * config/aarch64/aarch64.cc (aarch64_sve_move_pred_via_while): ++ Return a VNx16BI predicate. ++ ++2025-08-18 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-12 Richard Sandiford ++ ++ PR rtl-optimization/121253 ++ * fwprop.cc (forward_propagate_into): Don't propagate asm defs. ++ ++2025-08-15 Pengfei Li ++ ++ PR target/121449 ++ * config/aarch64/aarch64-sve.md ++ (mask_gather_load): Use vg ++ constraints for alternatives with immediate offset. ++ (mask_scatter_store): Likewise. ++ ++2025-08-15 Richard Sandiford ++ ++ Backported from master: ++ 2025-07-17 Richard Sandiford ++ Yury Khrustalev ++ ++ * doc/sourcebuild.texi (aarch64_sme_hw): Document. ++ ++2025-08-15 Lulu Cheng ++ ++ Backported from master: ++ 2025-08-15 Lulu Cheng ++ ++ PR target/121542 ++ * config/loongarch/loongarch.cc ++ (loongarch_vector_costs::add_stmt_cost): When using vectype, ++ first determine whether it is NULL. ++ ++2025-08-14 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-14 Richard Sandiford ++ ++ PR target/121414 ++ * config/aarch64/aarch64.cc (aarch64_is_variant_pcs): New function, ++ split out from... ++ (aarch64_asm_output_variant_pcs): ...here. Handle various types ++ of SME function type. ++ ++2025-08-14 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-14 Richard Sandiford ++ ++ PR target/121294 ++ * config/aarch64/aarch64.md (UNSPEC_REV_PRED): New unspec. ++ * config/aarch64/aarch64-sve.md (@aarch64_sve_rev_acle) ++ (*aarch64_sve_rev_acle): New patterns. ++ * config/aarch64/aarch64-sve-builtins-base.cc ++ (svrev_impl::expand): Use the new patterns for boolean svrev. ++ ++2025-08-14 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-14 Richard Sandiford ++ ++ PR target/121294 ++ * config/aarch64/iterators.md (UNSPEC_TRN1_CONV): Delete. ++ (UNSPEC_PERMUTE_PRED): New unspec. ++ * config/aarch64/aarch64-sve.md (@aarch64_sve_trn1_conv): ++ Replace with... ++ (@aarch64_sve__acle) ++ (*aarch64_sve__acle): ...these new patterns. ++ * config/aarch64/aarch64.cc (aarch64_expand_sve_const_pred_trn): ++ Update accordingly. ++ * config/aarch64/aarch64-sve-builtins-functions.h ++ (binary_permute::expand): Use the new _acle patterns for ++ predicate operations. ++ ++2025-08-14 H.J. Lu ++ ++ Backported from master: ++ 2025-07-28 H.J. Lu ++ ++ PR target/121208 ++ * config/i386/i386.cc (ix86_tls_get_addr): Issue an error for ++ -mtls-dialect=gnu with no_caller_saved_registers attribute and ++ suggest -mtls-dialect=gnu2. ++ ++2025-08-13 Lulu Cheng ++ ++ Backported from master: ++ 2025-08-13 Lulu Cheng ++ ++ PR target/120476 ++ * config/loongarch/loongarch.cc ++ (loongarch_compute_pressure_classes): New function. ++ (TARGET_COMPUTE_PRESSURE_CLASSES): Define. ++ ++2025-08-12 mengqinggang ++ ++ Backported from master: ++ 2025-08-12 mengqinggang ++ ++ * config/loongarch/loongarch-def.h (ABI_BASE_LP64D): New macro. ++ (ABI_BASE_LP64F): New macro. ++ (ABI_BASE_LP64S): New macro. ++ (N_ABI_BASE_TYPES): New macro. ++ +2025-08-08 Jakub Jelinek + + Backported from master: @@ -416,7 +556,7 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ +++ b/src/gcc/DATESTAMP @@ -1 +1 @@ -20250523 -+20250810 ++20250829 --- a/src/gcc/ada/ChangeLog +++ b/src/gcc/ada/ChangeLog @@ -1,3 +1,20 @@ @@ -817,8 +957,128 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ (clobber (reg:DI R0_REGNUM)) (clobber (reg:DI R14_REGNUM)) (clobber (reg:DI R15_REGNUM)) +--- a/src/gcc/config/aarch64/aarch64-sve-builtins-base.cc ++++ b/src/gcc/config/aarch64/aarch64-sve-builtins-base.cc +@@ -2396,7 +2396,10 @@ public: + rtx + expand (function_expander &e) const override + { +- return e.use_exact_insn (code_for_aarch64_sve_rev (e.vector_mode (0))); ++ auto mode = e.vector_mode (0); ++ return e.use_exact_insn (e.type_suffix (0).bool_p ++ ? code_for_aarch64_sve_rev_acle (mode) ++ : code_for_aarch64_sve_rev (mode)); + } + }; + +--- a/src/gcc/config/aarch64/aarch64-sve-builtins-functions.h ++++ b/src/gcc/config/aarch64/aarch64-sve-builtins-functions.h +@@ -615,7 +615,10 @@ public: + rtx + expand (function_expander &e) const override + { +- insn_code icode = code_for_aarch64_sve (m_unspec, e.vector_mode (0)); ++ auto mode = e.vector_mode (0); ++ insn_code icode = (e.type_suffix (0).bool_p ++ ? code_for_aarch64_sve_acle (m_unspec, mode) ++ : code_for_aarch64_sve (m_unspec, mode)); + return e.use_exact_insn (icode); + } + --- a/src/gcc/config/aarch64/aarch64-sve.md +++ b/src/gcc/config/aarch64/aarch64-sve.md +@@ -1458,18 +1458,18 @@ (define_insn "mask_gather_load" + UNSPEC_LD1_GATHER))] + "TARGET_SVE && TARGET_NON_STREAMING" + {@ [cons: =0, 1, 2, 3, 4, 5 ] +- [&w, Z, w, Ui1, Ui1, Upl] ld1\t%0.s, %5/z, [%2.s] +- [?w, Z, 0, Ui1, Ui1, Upl] ^ +- [&w, vgw, w, Ui1, Ui1, Upl] ld1\t%0.s, %5/z, [%2.s, #%1] +- [?w, vgw, 0, Ui1, Ui1, Upl] ^ +- [&w, rk, w, Z, Ui1, Upl] ld1\t%0.s, %5/z, [%1, %2.s, sxtw] +- [?w, rk, 0, Z, Ui1, Upl] ^ +- [&w, rk, w, Ui1, Ui1, Upl] ld1\t%0.s, %5/z, [%1, %2.s, uxtw] +- [?w, rk, 0, Ui1, Ui1, Upl] ^ +- [&w, rk, w, Z, i, Upl] ld1\t%0.s, %5/z, [%1, %2.s, sxtw %p4] +- [?w, rk, 0, Z, i, Upl] ^ +- [&w, rk, w, Ui1, i, Upl] ld1\t%0.s, %5/z, [%1, %2.s, uxtw %p4] +- [?w, rk, 0, Ui1, i, Upl] ^ ++ [&w, Z, w, Ui1, Ui1, Upl] ld1\t%0.s, %5/z, [%2.s] ++ [?w, Z, 0, Ui1, Ui1, Upl] ^ ++ [&w, vg, w, Ui1, Ui1, Upl] ld1\t%0.s, %5/z, [%2.s, #%1] ++ [?w, vg, 0, Ui1, Ui1, Upl] ^ ++ [&w, rk, w, Z, Ui1, Upl] ld1\t%0.s, %5/z, [%1, %2.s, sxtw] ++ [?w, rk, 0, Z, Ui1, Upl] ^ ++ [&w, rk, w, Ui1, Ui1, Upl] ld1\t%0.s, %5/z, [%1, %2.s, uxtw] ++ [?w, rk, 0, Ui1, Ui1, Upl] ^ ++ [&w, rk, w, Z, i, Upl] ld1\t%0.s, %5/z, [%1, %2.s, sxtw %p4] ++ [?w, rk, 0, Z, i, Upl] ^ ++ [&w, rk, w, Ui1, i, Upl] ld1\t%0.s, %5/z, [%1, %2.s, uxtw %p4] ++ [?w, rk, 0, Ui1, i, Upl] ^ + } + ) + +@@ -1487,14 +1487,14 @@ (define_insn "mask_gather_load" + UNSPEC_LD1_GATHER))] + "TARGET_SVE && TARGET_NON_STREAMING" + {@ [cons: =0, 1, 2, 3, 4, 5] +- [&w, Z, w, i, Ui1, Upl] ld1\t%0.d, %5/z, [%2.d] +- [?w, Z, 0, i, Ui1, Upl] ^ +- [&w, vgd, w, i, Ui1, Upl] ld1\t%0.d, %5/z, [%2.d, #%1] +- [?w, vgd, 0, i, Ui1, Upl] ^ +- [&w, rk, w, i, Ui1, Upl] ld1\t%0.d, %5/z, [%1, %2.d] +- [?w, rk, 0, i, Ui1, Upl] ^ +- [&w, rk, w, i, i, Upl] ld1\t%0.d, %5/z, [%1, %2.d, lsl %p4] +- [?w, rk, 0, i, i, Upl] ^ ++ [&w, Z, w, i, Ui1, Upl] ld1\t%0.d, %5/z, [%2.d] ++ [?w, Z, 0, i, Ui1, Upl] ^ ++ [&w, vg, w, i, Ui1, Upl] ld1\t%0.d, %5/z, [%2.d, #%1] ++ [?w, vg, 0, i, Ui1, Upl] ^ ++ [&w, rk, w, i, Ui1, Upl] ld1\t%0.d, %5/z, [%1, %2.d] ++ [?w, rk, 0, i, Ui1, Upl] ^ ++ [&w, rk, w, i, i, Upl] ld1\t%0.d, %5/z, [%1, %2.d, lsl %p4] ++ [?w, rk, 0, i, i, Upl] ^ + } + ) + +@@ -2378,13 +2378,13 @@ (define_insn "mask_scatter_store" + (match_operand:SVE_4 4 "register_operand")] + UNSPEC_ST1_SCATTER))] + "TARGET_SVE && TARGET_NON_STREAMING" +- {@ [ cons: 0 , 1 , 2 , 3 , 4 , 5 ] +- [ Z , w , Ui1 , Ui1 , w , Upl ] st1\t%4.s, %5, [%1.s] +- [ vgw , w , Ui1 , Ui1 , w , Upl ] st1\t%4.s, %5, [%1.s, #%0] +- [ rk , w , Z , Ui1 , w , Upl ] st1\t%4.s, %5, [%0, %1.s, sxtw] +- [ rk , w , Ui1 , Ui1 , w , Upl ] st1\t%4.s, %5, [%0, %1.s, uxtw] +- [ rk , w , Z , i , w , Upl ] st1\t%4.s, %5, [%0, %1.s, sxtw %p3] +- [ rk , w , Ui1 , i , w , Upl ] st1\t%4.s, %5, [%0, %1.s, uxtw %p3] ++ {@ [ cons: 0 , 1 , 2 , 3 , 4 , 5 ] ++ [ Z , w , Ui1 , Ui1 , w , Upl ] st1\t%4.s, %5, [%1.s] ++ [ vg , w , Ui1 , Ui1 , w , Upl ] st1\t%4.s, %5, [%1.s, #%0] ++ [ rk , w , Z , Ui1 , w , Upl ] st1\t%4.s, %5, [%0, %1.s, sxtw] ++ [ rk , w , Ui1 , Ui1 , w , Upl ] st1\t%4.s, %5, [%0, %1.s, uxtw] ++ [ rk , w , Z , i , w , Upl ] st1\t%4.s, %5, [%0, %1.s, sxtw %p3] ++ [ rk , w , Ui1 , i , w , Upl ] st1\t%4.s, %5, [%0, %1.s, uxtw %p3] + } + ) + +@@ -2401,11 +2401,11 @@ (define_insn "mask_scatter_store" + (match_operand:SVE_2 4 "register_operand")] + UNSPEC_ST1_SCATTER))] + "TARGET_SVE && TARGET_NON_STREAMING" +- {@ [ cons: 0 , 1 , 3 , 4 , 5 ] +- [ Z , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%1.d] +- [ vgd , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%1.d, #%0] +- [ rk , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%0, %1.d] +- [ rk , w , i , w , Upl ] st1\t%4.d, %5, [%0, %1.d, lsl %p3] ++ {@ [ cons: 0 , 1 , 3 , 4 , 5 ] ++ [ Z , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%1.d] ++ [ vg , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%1.d, #%0] ++ [ rk , w , Ui1 , w , Upl ] st1\t%4.d, %5, [%0, %1.d] ++ [ rk , w , i , w , Upl ] st1\t%4.d, %5, [%0, %1.d, lsl %p3] + } + ) + @@ -6422,10 +6422,10 @@ (define_expand "@aarch64_frecps" ;; by providing this, but we need to use UNSPECs since rtx logical ops ;; aren't defined for floating-point modes. @@ -834,7 +1094,87 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ LOGICALF))] "TARGET_SVE" "\t%0.d, %1.d, %2.d" -@@ -10989,16 +10989,12 @@ (define_insn_and_split "@aarch64_sve_get_neonq_" +@@ -9123,7 +9123,30 @@ (define_insn "@aarch64_sve_rev" + (unspec:PRED_ALL [(match_operand:PRED_ALL 1 "register_operand" "Upa")] + UNSPEC_REV))] + "TARGET_SVE" +- "rev\t%0., %1.") ++ "rev\t%0., %1." ++) ++ ++(define_expand "@aarch64_sve_rev_acle" ++ [(set (match_operand:VNx16BI 0 "register_operand") ++ (unspec:VNx16BI ++ [(match_operand:VNx16BI 1 "register_operand") ++ (match_dup:PRED_ALL 2)] ++ UNSPEC_REV_PRED))] ++ "TARGET_SVE" ++ { ++ operands[2] = CONST0_RTX (mode); ++ } ++) ++ ++(define_insn "*aarch64_sve_rev_acle" ++ [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") ++ (unspec:VNx16BI ++ [(match_operand:VNx16BI 1 "register_operand" "Upa") ++ (match_operand:PRED_ALL 2 "aarch64_simd_imm_zero")] ++ UNSPEC_REV_PRED))] ++ "TARGET_SVE" ++ "rev\t%0., %1." ++) + + ;; ------------------------------------------------------------------------- + ;; ---- [PRED] Special-purpose binary permutes +@@ -9148,18 +9171,39 @@ (define_insn "@aarch64_sve_" + "\t%0., %1., %2." + ) + +-;; Special purpose permute used by the predicate generation instructions. +-;; Unlike the normal permute patterns, these instructions operate on VNx16BI +-;; regardless of the element size, so that all input and output bits are +-;; well-defined. Operand 3 then indicates the size of the permute. +-(define_insn "@aarch64_sve_trn1_conv" ++;; Special-purpose permutes used by the ACLE intrinsics and predicate ++;; generation instructions. Unlike the normal permute patterns, these ++;; instructions operate on VNx16BI regardless of the element size, so that ++;; all input and output bits are well-defined. Operand 3 then indicates ++;; the size of the permute. ++;; ++;; To make generation easier, this pattern embeds the permute type as the ++;; fourth operand to the unspec. On the one hand, this avoids overloading ++;; unspecs like UNSPEC_ZIP1 to represent two different operations. On the ++;; other hand, it avoids having a separate unspec for each variant, and ++;; having to map from one kind of unspec to the other. ++(define_expand "@aarch64_sve__acle" ++ [(set (match_operand:VNx16BI 0 "register_operand") ++ (unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand") ++ (match_operand:VNx16BI 2 "register_operand") ++ (match_dup:PRED_ALL 3) ++ (const_int PERMUTE)] ++ UNSPEC_PERMUTE_PRED))] ++ "TARGET_SVE" ++ { ++ operands[3] = CONST0_RTX (mode); ++ } ++) ++ ++(define_insn "*aarch64_sve__acle" + [(set (match_operand:VNx16BI 0 "register_operand" "=Upa") + (unspec:VNx16BI [(match_operand:VNx16BI 1 "register_operand" "Upa") + (match_operand:VNx16BI 2 "register_operand" "Upa") +- (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero")] +- UNSPEC_TRN1_CONV))] ++ (match_operand:PRED_ALL 3 "aarch64_simd_imm_zero") ++ (const_int PERMUTE)] ++ UNSPEC_PERMUTE_PRED))] + "TARGET_SVE" +- "trn1\t%0., %1., %2." ++ "\t%0., %1., %2." + ) + + ;; ========================================================================= +@@ -10989,16 +11033,12 @@ (define_insn_and_split "@aarch64_sve_get_neonq_" (define_insn "@aarch64_sve_set_neonq_" [(set (match_operand:SVE_FULL 0 "register_operand" "=w") @@ -859,7 +1199,26 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ ) --- a/src/gcc/config/aarch64/aarch64.cc +++ b/src/gcc/config/aarch64/aarch64.cc -@@ -24019,6 +24019,13 @@ aarch64_expand_vector_init (rtx target, rtx vals) +@@ -5679,7 +5679,7 @@ aarch64_sve_move_pred_via_while (rtx target, machine_mode mode, + target = aarch64_target_reg (target, mode); + emit_insn (gen_while (UNSPEC_WHILELO, DImode, mode, + target, const0_rtx, limit)); +- return target; ++ return gen_lowpart (VNx16BImode, target); + } + + static rtx +@@ -5824,8 +5824,7 @@ aarch64_expand_sve_const_pred_trn (rtx target, rtx_vector_builder &builder, + operands but permutes them as though they had mode MODE. */ + machine_mode mode = aarch64_sve_pred_mode (permute_size).require (); + target = aarch64_target_reg (target, GET_MODE (a)); +- rtx type_reg = CONST0_RTX (mode); +- emit_insn (gen_aarch64_sve_trn1_conv (mode, target, a, b, type_reg)); ++ emit_insn (gen_aarch64_sve_acle (UNSPEC_TRN1, mode, target, a, b)); + return target; + } + +@@ -24019,6 +24018,13 @@ aarch64_expand_vector_init (rtx target, rtx vals) emit_insn (rec_seq); } @@ -873,7 +1232,57 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ rtvec v = gen_rtvec (2, halves[0], halves[1]); rtx_insn *zip1_insn = emit_set_insn (target, gen_rtx_UNSPEC (mode, v, UNSPEC_ZIP1)); -@@ -25934,12 +25941,23 @@ aarch64_evpc_tbl (struct expand_vec_perm_d *d) +@@ -24432,20 +24438,41 @@ aarch64_asm_preferred_eh_data_format (int code ATTRIBUTE_UNUSED, int global) + return (global ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | type; + } + ++/* Return true if function declaration FNDECL needs to be marked as ++ having a variant PCS. */ ++ ++static bool ++aarch64_is_variant_pcs (tree fndecl) ++{ ++ /* Check for ABIs that preserve more registers than usual. */ ++ arm_pcs pcs = (arm_pcs) fndecl_abi (fndecl).id (); ++ if (pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE) ++ return true; ++ ++ /* Check for ABIs that allow PSTATE.SM to be 1 on entry. */ ++ tree fntype = TREE_TYPE (fndecl); ++ if (aarch64_fntype_pstate_sm (fntype) != AARCH64_FL_SM_OFF) ++ return true; ++ ++ /* Check for ABIs that require PSTATE.ZA to be 1 on entry, either because ++ of ZA or ZT0. */ ++ if (aarch64_fntype_pstate_za (fntype) != 0) ++ return true; ++ ++ return false; ++} ++ + /* Output .variant_pcs for aarch64_vector_pcs function symbols. */ + + static void + aarch64_asm_output_variant_pcs (FILE *stream, const tree decl, const char* name) + { +- if (TREE_CODE (decl) == FUNCTION_DECL) ++ if (TREE_CODE (decl) == FUNCTION_DECL ++ && aarch64_is_variant_pcs (decl)) + { +- arm_pcs pcs = (arm_pcs) fndecl_abi (decl).id (); +- if (pcs == ARM_PCS_SIMD || pcs == ARM_PCS_SVE) +- { +- fprintf (stream, "\t.variant_pcs\t"); +- assemble_name (stream, name); +- fprintf (stream, "\n"); +- } ++ fprintf (stream, "\t.variant_pcs\t"); ++ assemble_name (stream, name); ++ fprintf (stream, "\n"); + } + } + +@@ -25934,12 +25961,23 @@ aarch64_evpc_tbl (struct expand_vec_perm_d *d) static bool aarch64_evpc_sve_tbl (struct expand_vec_perm_d *d) { @@ -919,6 +1328,14 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ (SME_STATE_REGNUM 88) ;; Instructions write to this register if they set TPIDR2_EL0 to a +@@ -259,6 +267,7 @@ (define_c_enum "unspec" [ + UNSPEC_PACIBSP + UNSPEC_PRLG_STK + UNSPEC_REV ++ UNSPEC_REV_PRED + UNSPEC_RBIT + UNSPEC_SADALP + UNSPEC_SCVTF --- a/src/gcc/config/aarch64/iterators.md +++ b/src/gcc/config/aarch64/iterators.md @@ -519,15 +519,20 @@ (define_mode_iterator SVE_PARTIAL_I [VNx8QI VNx4QI VNx2QI @@ -963,6 +1380,24 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ ;; All SVE integer vector modes and Advanced SIMD 64-bit vector ;; element modes (define_mode_iterator SVE_I_SIMD_DI [SVE_I V2DI]) +@@ -824,7 +823,6 @@ (define_c_enum "unspec" + UNSPEC_UZP2Q ; Used in aarch64-sve.md. + UNSPEC_ZIP1Q ; Used in aarch64-sve.md. + UNSPEC_ZIP2Q ; Used in aarch64-sve.md. +- UNSPEC_TRN1_CONV ; Used in aarch64-sve.md. + UNSPEC_COND_CMPEQ_WIDE ; Used in aarch64-sve.md. + UNSPEC_COND_CMPGE_WIDE ; Used in aarch64-sve.md. + UNSPEC_COND_CMPGT_WIDE ; Used in aarch64-sve.md. +@@ -1054,6 +1052,9 @@ (define_c_enum "unspec" + UNSPEC_BFCVT ; Used in aarch64-simd.md. + UNSPEC_FCVTXN ; Used in aarch64-simd.md. + ++ ;; All used in aarch64-sve.md ++ UNSPEC_PERMUTE_PRED ++ + ;; All used in aarch64-sve2.md + UNSPEC_FCVTN + UNSPEC_FDOT --- a/src/gcc/config/avr/avr-mcus.def +++ b/src/gcc/config/avr/avr-mcus.def @@ -313,6 +313,10 @@ AVR_MCU ("avr64da28", ARCH_AVRXMEGA2, AVR_ISA_FLMAP, "__AVR_AVR64DA28__", @@ -997,9 +1432,49 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ AVR_MCU ("avr128db28", ARCH_AVRXMEGA4, AVR_ISA_FLMAP, "__AVR_AVR128DB28__", 0x4000, 0x0, 0x20000, 0) AVR_MCU ("avr128db32", ARCH_AVRXMEGA4, AVR_ISA_FLMAP, "__AVR_AVR128DB32__", 0x4000, 0x0, 0x20000, 0) AVR_MCU ("avr128db48", ARCH_AVRXMEGA4, AVR_ISA_FLMAP, "__AVR_AVR128DB48__", 0x4000, 0x0, 0x20000, 0) +--- a/src/gcc/config/avr/specs.h ++++ b/src/gcc/config/avr/specs.h +@@ -57,7 +57,7 @@ along with GCC; see the file COPYING3. If not see + "%(asm_errata_skip) " + + #define LINK_RELAX_SPEC \ +- "%{mrelax:--relax} " ++ "%{!r:%{mrelax:--relax}} " + + #undef LINK_SPEC + #define LINK_SPEC \ --- a/src/gcc/config/i386/i386.cc +++ b/src/gcc/config/i386/i386.cc -@@ -12218,11 +12218,12 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov) +@@ -12119,6 +12119,28 @@ static GTY(()) rtx ix86_tls_symbol; + static rtx + ix86_tls_get_addr (void) + { ++ if (cfun->machine->call_saved_registers ++ == TYPE_NO_CALLER_SAVED_REGISTERS) ++ { ++ /* __tls_get_addr doesn't preserve vector registers. When a ++ function with no_caller_saved_registers attribute calls ++ __tls_get_addr, YMM and ZMM registers will be clobbered. ++ Issue an error and suggest -mtls-dialect=gnu2 in this case. */ ++ if (cfun->machine->func_type == TYPE_NORMAL) ++ error (G_("%<-mtls-dialect=gnu2%> must be used with a function" ++ " with the % attribute")); ++ else ++ error (cfun->machine->func_type == TYPE_EXCEPTION ++ ? G_("%<-mtls-dialect=gnu2%> must be used with an" ++ " exception service routine") ++ : G_("%<-mtls-dialect=gnu2%> must be used with an" ++ " interrupt service routine")); ++ /* Don't issue the same error twice. */ ++ cfun->machine->func_type = TYPE_NORMAL; ++ cfun->machine->call_saved_registers ++ = TYPE_DEFAULT_CALL_SAVED_REGISTERS; ++ } ++ + if (!ix86_tls_symbol) + { + const char *sym +@@ -12218,11 +12240,12 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov) if (TARGET_64BIT) { rtx rax = gen_rtx_REG (Pmode, AX_REG); @@ -1013,7 +1488,7 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ insns = get_insns (); end_sequence (); -@@ -12272,12 +12273,13 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov) +@@ -12272,12 +12295,13 @@ legitimize_tls_address (rtx x, enum tls_model model, bool for_mov) if (TARGET_64BIT) { rtx rax = gen_rtx_REG (Pmode, AX_REG); @@ -1236,9 +1711,36 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ (match_operand:LASX_DWH 2 "register_operand" "f") (match_operand:LASX_DWH 3 "register_operand" "f")] UNSPEC_LASX_XVSHUF))] +--- a/src/gcc/config/loongarch/loongarch-def.h ++++ b/src/gcc/config/loongarch/loongarch-def.h +@@ -78,12 +78,10 @@ extern loongarch_def_array + + + /* Base ABI */ +-enum { +- ABI_BASE_LP64D = 0, +- ABI_BASE_LP64F = 1, +- ABI_BASE_LP64S = 2, +- N_ABI_BASE_TYPES = 3 +-}; ++#define ABI_BASE_LP64D 0 ++#define ABI_BASE_LP64F 1 ++#define ABI_BASE_LP64S 2 ++#define N_ABI_BASE_TYPES 3 + + extern loongarch_def_array + loongarch_abi_base_strings; --- a/src/gcc/config/loongarch/loongarch.cc +++ b/src/gcc/config/loongarch/loongarch.cc -@@ -8199,7 +8199,7 @@ static bool +@@ -4280,6 +4280,7 @@ loongarch_vector_costs::add_stmt_cost (int count, vect_cost_for_stmt kind, + break; + } + else if (TARGET_RECIP_VEC_DIV ++ && vectype + && gimple_code (stmt_info->stmt) == GIMPLE_ASSIGN) + { + machine_mode mode = TYPE_MODE (vectype); +@@ -8199,7 +8200,7 @@ static bool loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d) { int i; @@ -1247,7 +1749,7 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ rtx rperm[MAX_VECT_LEN]; if (GET_MODE_SIZE (d->vmode) == 16) -@@ -8218,47 +8218,23 @@ loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d) +@@ -8218,47 +8219,23 @@ loongarch_try_expand_lsx_vshuf_const (struct expand_vec_perm_d *d) for (i = 0; i < d->nelt; i += 1) rperm[i] = GEN_INT (d->perm[i]); @@ -1311,7 +1813,7 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ return true; } -@@ -9254,7 +9230,7 @@ loongarch_expand_vec_perm_const (struct expand_vec_perm_d *d) +@@ -9254,7 +9231,7 @@ loongarch_expand_vec_perm_const (struct expand_vec_perm_d *d) bool flag = false; unsigned int i; unsigned char idx; @@ -1320,7 +1822,7 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ rtx rperm[MAX_VECT_LEN]; unsigned int remapped[MAX_VECT_LEN]; unsigned char perm2[MAX_VECT_LEN]; -@@ -9434,63 +9410,23 @@ loongarch_expand_vec_perm_const (struct expand_vec_perm_d *d) +@@ -9434,63 +9411,23 @@ loongarch_expand_vec_perm_const (struct expand_vec_perm_d *d) expand_perm_const_end: if (flag) { @@ -1397,6 +1899,35 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ return true; } +@@ -11014,6 +10951,18 @@ loongarch_c_mode_for_suffix (char suffix) + return VOIDmode; + } + ++/* Implement TARGET_COMPUTE_PRESSURE_CLASSES. */ ++ ++static int ++loongarch_compute_pressure_classes (reg_class *classes) ++{ ++ int i = 0; ++ classes[i++] = GENERAL_REGS; ++ classes[i++] = FP_REGS; ++ classes[i++] = FCC_REGS; ++ return i; ++} ++ + /* Initialize the GCC target structure. */ + #undef TARGET_ASM_ALIGNED_HI_OP + #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" +@@ -11276,6 +11225,9 @@ loongarch_c_mode_for_suffix (char suffix) + #undef TARGET_C_MODE_FOR_SUFFIX + #define TARGET_C_MODE_FOR_SUFFIX loongarch_c_mode_for_suffix + ++#undef TARGET_COMPUTE_PRESSURE_CLASSES ++#define TARGET_COMPUTE_PRESSURE_CLASSES loongarch_compute_pressure_classes ++ + struct gcc_target targetm = TARGET_INITIALIZER; + + #include "gt-loongarch.h" --- a/src/gcc/config/loongarch/lsx.md +++ b/src/gcc/config/loongarch/lsx.md @@ -689,9 +689,9 @@ (define_expand "vec_perm" @@ -2241,7 +2772,33 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ /* Perform the decimal floating point operation described by CODE. --- a/src/gcc/fortran/ChangeLog +++ b/src/gcc/fortran/ChangeLog -@@ -1,3 +1,30 @@ +@@ -1,3 +1,56 @@ ++2025-08-22 Harald Anlauf ++ ++ Backported from master: ++ 2025-07-18 Harald Anlauf ++ ++ PR fortran/121145 ++ * trans-expr.cc (gfc_conv_procedure_call): Do not create pointer ++ check for proc-pointer actual passed to optional dummy. ++ ++2025-08-22 Harald Anlauf ++ ++ Backported from master: ++ 2025-06-27 Harald Anlauf ++ ++ PR fortran/120784 ++ * interface.cc (gfc_match_end_interface): Detect empty local_name. ++ ++2025-08-22 Harald Anlauf ++ ++ Backported from master: ++ 2025-06-23 Harald Anlauf ++ ++ PR fortran/120784 ++ * interface.cc (gfc_match_end_interface): If a use-associated ++ symbol is renamed, use the local_name for checking. ++ +2025-07-16 Paul Thomas + + Backported from master: @@ -2274,7 +2831,31 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ * GCC 14.3.0 released. --- a/src/gcc/fortran/interface.cc +++ b/src/gcc/fortran/interface.cc -@@ -4622,6 +4622,13 @@ matching_typebound_op (gfc_expr** tb_base, +@@ -452,11 +452,20 @@ gfc_match_end_interface (void) + + case INTERFACE_DTIO: + case INTERFACE_GENERIC: ++ /* If a use-associated symbol is renamed, check the local_name. */ ++ const char *local_name = current_interface.sym->name; ++ ++ if (current_interface.sym->attr.use_assoc ++ && current_interface.sym->attr.use_rename ++ && current_interface.sym->ns->use_stmts->rename ++ && (current_interface.sym->ns->use_stmts->rename->local_name[0] ++ != '\0')) ++ local_name = current_interface.sym->ns->use_stmts->rename->local_name; ++ + if (type != current_interface.type +- || strcmp (current_interface.sym->name, name) != 0) ++ || strcmp (local_name, name) != 0) + { +- gfc_error ("Expecting % at %C", +- current_interface.sym->name); ++ gfc_error ("Expecting % at %C", local_name); + m = MATCH_ERROR; + } + +@@ -4622,6 +4631,13 @@ matching_typebound_op (gfc_expr** tb_base, gfc_actual_arglist* argcopy; bool matches; @@ -2301,6 +2882,41 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ else if (a->function && sym->result && a->access != ACCESS_PRIVATE && (sym->ts.u.derived->attr.alloc_comp || sym->ts.u.derived->attr.pointer_comp)) +--- a/src/gcc/fortran/trans-expr.cc ++++ b/src/gcc/fortran/trans-expr.cc +@@ -7717,7 +7717,8 @@ gfc_conv_procedure_call (gfc_se * se, gfc_symbol * sym, + msg = xasprintf ("Pointer actual argument '%s' is not " + "associated", e->symtree->n.sym->name); + else if (attr.proc_pointer && !e->value.function.actual +- && (fsym == NULL || !fsym_attr.proc_pointer)) ++ && (fsym == NULL ++ || (!fsym_attr.proc_pointer && !fsym_attr.optional))) + msg = xasprintf ("Proc-pointer actual argument '%s' is not " + "associated", e->symtree->n.sym->name); + else +--- a/src/gcc/fwprop.cc ++++ b/src/gcc/fwprop.cc +@@ -842,6 +842,20 @@ forward_propagate_into (use_info *use, bool reg_prop_only = false) + if (def_insn->is_artificial ()) + return false; + ++ /* Do not propagate asms. The only kind of propagation that would ++ succeed is propagation into a register move. Such a propagation ++ is neutral if the destination of the move is a pseudo and unnecessarily ++ restricts the register allocator if the destination of the move is ++ a hard register. ++ ++ Furthermore, unlike for a normal instruction, we cannot take a SET from an ++ asm and try dropping the CLOBBERs. The recog process does not (and should ++ not try to) second-guess whether what the user wrote can be changed and ++ so it has to assume that any asm given to it is a fair reflection of ++ what the user wrote. */ ++ if (def_insn->is_asm ()) ++ return false; ++ + rtx_insn *def_rtl = def_insn->rtl (); + if (!NONJUMP_INSN_P (def_rtl)) + return false; --- a/src/gcc/gimple-fold.cc +++ b/src/gcc/gimple-fold.cc @@ -936,6 +936,8 @@ gimple_fold_builtin_memory_op (gimple_stmt_iterator *gsi, @@ -2943,7 +3559,155 @@ LANG=C git diff --no-renames --src-prefix=a/src/ --dst-prefix=b/src/ \ /* Returns 10**2**N. */ --- a/src/gcc/testsuite/ChangeLog +++ b/src/gcc/testsuite/ChangeLog -@@ -1,3 +1,348 @@ +@@ -1,3 +1,496 @@ ++2025-08-22 Harald Anlauf ++ ++ Backported from master: ++ 2025-07-18 Harald Anlauf ++ ++ PR fortran/121145 ++ * gfortran.dg/pointer_check_15.f90: New test. ++ ++2025-08-22 Harald Anlauf ++ ++ Backported from master: ++ 2025-06-27 Harald Anlauf ++ ++ PR fortran/120784 ++ * gfortran.dg/interface_63.f90: Extend testcase. ++ ++2025-08-22 Harald Anlauf ++ ++ Backported from master: ++ 2025-06-23 Harald Anlauf ++ ++ PR fortran/120784 ++ * gfortran.dg/interface_63.f90: New test. ++ ++2025-08-20 Martin Jambor ++ ++ Backported from master: ++ 2025-07-23 Martin Jambor ++ ++ PR tree-optimization/119085 ++ * gcc.dg/tree-ssa/pr119085.c: New test. ++ ++2025-08-20 Martin Jambor ++ ++ Backported from master: ++ 2025-07-18 Martin Jambor ++ ++ PR tree-optimization/117423 ++ * gcc.dg/tree-ssa/pr117423.c: New test. ++ ++2025-08-18 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-18 Richard Sandiford ++ ++ PR target/121118 ++ * gcc.target/aarch64/sve/acle/general/pr121118_1.c: New test. ++ ++2025-08-18 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-12 Richard Sandiford ++ ++ PR rtl-optimization/121253 ++ * gcc.target/aarch64/pr121253.c: New test. ++ ++2025-08-15 Pengfei Li ++ ++ PR target/121449 ++ * g++.target/aarch64/sve/pr121449.C: New test. ++ ++2025-08-15 Richard Sandiford ++ ++ Backported from master: ++ 2025-07-17 Richard Sandiford ++ Yury Khrustalev ++ ++ * lib/target-supports.exp (add_options_for_aarch64_sme) ++ (check_effective_target_aarch64_sme_hw): New procedures. ++ * g++.target/aarch64/sme/sme_throw_1.C: New test. ++ * g++.target/aarch64/sme/sme_throw_2.C: Likewise. ++ ++2025-08-15 Lulu Cheng ++ ++ Backported from master: ++ 2025-08-15 Lulu Cheng ++ ++ PR target/121542 ++ * gcc.target/loongarch/pr121542.c: New test. ++ ++2025-08-14 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-14 Richard Sandiford ++ ++ PR target/121414 ++ * gcc.target/aarch64/sme/pr121414_1.c: New test. ++ ++2025-08-14 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-14 Richard Sandiford ++ ++ PR target/121294 ++ * gcc.target/aarch64/sve/acle/general/rev_2.c: New test. ++ ++2025-08-14 Richard Sandiford ++ ++ Backported from master: ++ 2025-08-14 Richard Sandiford ++ ++ PR target/121294 ++ * gcc.target/aarch64/sve/acle/general/perm_2.c: New test. ++ * gcc.target/aarch64/sve/acle/general/perm_3.c: Likewise. ++ * gcc.target/aarch64/sve/acle/general/perm_4.c: Likewise. ++ * gcc.target/aarch64/sve/acle/general/perm_5.c: Likewise. ++ * gcc.target/aarch64/sve/acle/general/perm_6.c: Likewise. ++ * gcc.target/aarch64/sve/acle/general/perm_7.c: Likewise. ++ ++2025-08-14 H.J. Lu ++ ++ Backported from master: ++ 2025-07-29 H.J. Lu ++ ++ PR target/121208 ++ * gcc.target/i386/pr121208-1a.c (dg-options): Add ++ -mno-sse -mno-mmx -mno-80387. ++ * gcc.target/i386/pr121208-1b.c (dg-options): Likewise. ++ ++2025-08-14 H.J. Lu ++ ++ Backported from master: ++ 2025-07-28 H.J. Lu ++ ++ PR target/121208 ++ * gcc.target/i386/pr121208-1a.c: New test. ++ * gcc.target/i386/pr121208-1b.c: Likewise. ++ * gcc.target/i386/pr121208-2a.c: Likewise. ++ * gcc.target/i386/pr121208-2b.c: Likewise. ++ * gcc.target/i386/pr121208-3a.c: Likewise. ++ * gcc.target/i386/pr121208-3b.c: Likewise. ++ ++2025-08-11 Alexandre Oliva ++ ++ Backported from master: ++ 2025-05-21 Alexandre Oliva ++ ++ * gcc.dg/vect/tsvc/vect-tsvc-s332.c: Require vect_early_break_hw. ++ * gcc.dg/vect/tsvc/vect-tsvc-s481.c: Likewise. ++ * gcc.dg/vect/tsvc/vect-tsvc-s482.c: Likewise. ++ ++2025-08-10 Torbjörn SVENSSON ++ ++ Backported from master: ++ 2025-08-10 Torbjörn SVENSSON ++ ++ * lib/multiline.exp: Added pruning of .exe. ++ +2025-08-08 Patrick Palka + + Backported from master: @@ -3659,6 +4423,122 @@ new file mode 100644 +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/g++.target/aarch64/sme/sme_throw_1.C +@@ -0,0 +1,56 @@ ++/* { dg-do run { target { aarch64*-linux-gnu* && aarch64_sme_hw } } } */ ++/* { dg-options "-fnon-call-exceptions" } */ ++ ++#include ++#include ++ ++static bool caught; ++ ++[[gnu::noipa]] void thrower(int) ++{ ++ throw 1; ++} ++ ++[[gnu::noipa]] void bar() ++{ ++ *(volatile int *)0 = 0; ++} ++ ++[[gnu::noipa]] void foo() ++{ ++ try ++ { ++ bar(); ++ } ++ catch (int) ++ { ++ caught = true; ++ } ++} ++ ++__arm_new("za") __arm_locally_streaming void sme_user() ++{ ++ svbool_t all = svptrue_b8(); ++ for (unsigned int i = 0; i < svcntb(); ++i) ++ { ++ svint8_t expected = svindex_s8(i + 1, i); ++ svwrite_hor_za8_m(0, i, all, expected); ++ } ++ foo(); ++ for (unsigned int i = 0; i < svcntb(); ++i) ++ { ++ svint8_t expected = svindex_s8(i + 1, i); ++ svint8_t actual = svread_hor_za8_m(svdup_s8(0), all, 0, i); ++ if (svptest_any(all, svcmpne(all, expected, actual))) ++ __builtin_abort(); ++ } ++ if (!caught) ++ __builtin_abort(); ++} ++ ++int main() ++{ ++ signal(SIGSEGV, thrower); ++ sme_user(); ++ return 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.target/aarch64/sme/sme_throw_2.C +@@ -0,0 +1,4 @@ ++/* { dg-do run { target { aarch64*-linux-gnu* && aarch64_sme_hw } } } */ ++/* { dg-options "-O2 -fnon-call-exceptions" } */ ++ ++#include "sme_throw_1.C" +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/g++.target/aarch64/sve/pr121449.C +@@ -0,0 +1,44 @@ ++/* PR target/121449 */ ++/* { dg-do assemble { target aarch64_asm_sve_ok } } */ ++/* { dg-options "-O3 -save-temps" } */ ++ ++struct example; ++ ++struct array { ++ unsigned length(); ++ example *operator[](unsigned i) { ++ example **data = reinterpret_cast(this); ++ return data[i]; ++ } ++}; ++ ++struct example { ++ int a[16]; ++ bool is_even; ++ int version; ++ int count() { return is_even ? 2 : 1; } ++ void fun1(int, long); ++ void fun2(unsigned, unsigned); ++ void process(array &, array &); ++}; ++ ++bool found; ++ ++void example::process(array &a, array &b) { ++ for (unsigned i = 1; a.length(); i++) { ++ long total = 0; ++ for (unsigned k = 0; k <= i; k++) { ++ total += a[k]->count(); ++ } ++ for (unsigned j = 0; j < i; j++) { ++ int major = b[j]->version; ++ if (found) ++ major += i; ++ fun1(i + 1, total); ++ fun2(j, major); ++ } ++ } ++} ++ ++/* { dg-final { scan-assembler-not {\tld1b\t(z[0-9]+)\.d, p[0-7]/z, \[(z[0-9]+)\.d, #64\]} } } */ ++ +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/g++.target/s390/pr119834.C @@ -0,0 +1,76 @@ +// PR target/119834 @@ -4146,6 +5026,100 @@ new file mode 100644 +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr117423.c +@@ -0,0 +1,49 @@ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ ++ ++struct s4 { ++ int _0; ++}; ++struct s1 { ++ unsigned char _4; ++ long _1; ++}; ++struct s2 { ++ union { ++ struct s3 { ++ unsigned char _1; ++ struct s4 _0; ++ } var_0; ++ struct s1 var_1; ++ } DATA; ++}; ++int f1(int arg0) { return arg0 > 12345; } ++__attribute__((noinline)) ++struct s4 f2(int arg0) { ++ struct s4 rv = {arg0}; ++ return rv; ++} ++struct s2 f3(int arg0) { ++ struct s2 rv; ++ struct s1 var6 = {0}; ++ struct s4 var7; ++ if (f1(arg0)) { ++ rv.DATA.var_1 = var6; ++ return rv; ++ } else { ++ rv.DATA.var_0._1 = 2; ++ var7 = f2(arg0); ++ rv.DATA.var_0._0 = var7; ++ return rv; ++ } ++} ++int main() { ++ if (f3(12345).DATA.var_0._0._0 == 12345) ++ ; ++ else ++ __builtin_abort(); ++ if (f3(12344).DATA.var_0._0._0 == 12344) ++ ; ++ else ++ __builtin_abort(); ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.dg/tree-ssa/pr119085.c +@@ -0,0 +1,37 @@ ++/* { dg-do run } */ ++/* { dg-options "-O1" } */ ++ ++struct with_hole { ++ int x; ++ long y; ++}; ++struct without_hole { ++ int x; ++ int y; ++}; ++union u { ++ struct with_hole with_hole; ++ struct without_hole without_hole; ++}; ++ ++void __attribute__((noinline)) ++test (union u *up, union u u) ++{ ++ union u u2; ++ volatile int f = 0; ++ u2 = u; ++ if (f) ++ u2.with_hole = u.with_hole; ++ *up = u2; ++} ++ ++int main(void) ++{ ++ union u u; ++ union u u2; ++ u2.without_hole.y = -1; ++ test (&u, u2); ++ if (u.without_hole.y != -1) ++ __builtin_abort (); ++ return 0; ++} +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.dg/ubsan/pr120837.c @@ -0,0 +1,32 @@ +/* PR c/120837 */ @@ -4180,6 +5154,56 @@ new file mode 100644 + if (foo (2, 1) != 0) + __builtin_abort (); +} +--- a/src/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s332.c ++++ b/src/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s332.c +@@ -3,6 +3,7 @@ + + /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ + /* { dg-require-effective-target vect_float } */ ++/* { dg-require-effective-target vect_early_break_hw } */ + /* { dg-add-options vect_early_break } */ + + #include "tsvc.h" +--- a/src/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s481.c ++++ b/src/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s481.c +@@ -3,6 +3,7 @@ + + /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ + /* { dg-require-effective-target vect_float } */ ++/* { dg-require-effective-target vect_early_break_hw } */ + /* { dg-add-options vect_early_break } */ + + #include "tsvc.h" +--- a/src/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s482.c ++++ b/src/gcc/testsuite/gcc.dg/vect/tsvc/vect-tsvc-s482.c +@@ -3,6 +3,7 @@ + + /* { dg-additional-options "--param vect-epilogues-nomask=0" } */ + /* { dg-require-effective-target vect_float } */ ++/* { dg-require-effective-target vect_early_break_hw } */ + /* { dg-add-options vect_early_break } */ + + #include "tsvc.h" +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/pr121253.c +@@ -0,0 +1,16 @@ ++/* { dg-options "-O" } */ ++ ++struct s128 { ++ long a, b; ++}; ++ ++struct s128 foo(void) { ++ struct s128 ret; ++ asm("mov %0, #0 \n\t" ++ "mov %R0, #0 \n\t" ++ "mov x0, #12345" ++ : "=r" (ret) : : "x0"); ++ return ret; ++} ++ ++/* { dg-final { scan-assembler-not {mov x0, #0} } } */ --- a/src/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c +++ b/src/gcc/testsuite/gcc.target/aarch64/sme/call_sm_switch_1.c @@ -1,5 +1,5 @@ @@ -4269,6 +5293,37 @@ new file mode 100644 +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sme/pr121414_1.c +@@ -0,0 +1,27 @@ ++#pragma GCC target "+sme2" ++ ++void f1() __arm_streaming_compatible {} ++void f2() __arm_streaming {} ++void f3() __arm_in("za") {} ++void f4() __arm_out("za") {} ++void f5() __arm_inout("za") {} ++void f6() __arm_in("zt0") {} ++void f7() __arm_out("zt0") {} ++void f8() __arm_inout("zt0") {} ++ ++__arm_locally_streaming void g1() {} ++__arm_new("za") void g2() {} ++__arm_new("zt0") void g3() {} ++ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf1\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf2\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf3\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf4\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf5\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf6\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf7\n} } } */ ++/* { dg-final { scan-assembler {\t\.variant_pcs\tf8\n} } } */ ++ ++/* { dg-final { scan-assembler-not {\t\.variant_pcs\tg1\n} } } */ ++/* { dg-final { scan-assembler-not {\t\.variant_pcs\tg2\n} } } */ ++/* { dg-final { scan-assembler-not {\t\.variant_pcs\tg3\n} } } */ +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/aarch64/sme/za_state_7.c @@ -0,0 +1,21 @@ +// { dg-options "-O -fno-optimize-sibling-calls -fomit-frame-pointer" } @@ -4312,6 +5367,657 @@ new file mode 100644 +/* { dg-final { scan-assembler-not {\ttbl\t} } } */ new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_2.c +@@ -0,0 +1,96 @@ ++/* { dg-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++** test1: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** trn1 p0\.h, p[0-3]\.h, \1\.h ++** ret ++*/ ++svbool_t ++test1 () ++{ ++ return svtrn1_b16 (svptrue_b8 (), svptrue_b16 ()); ++} ++ ++/* ++** test2: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** trn1 p0\.h, \1\.h, p[0-3]\.h ++** ret ++*/ ++svbool_t ++test2 () ++{ ++ return svtrn1_b16 (svptrue_b16 (), svptrue_b8 ()); ++} ++ ++/* ++** test3: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** trn1 p0\.s, p[0-3]\.s, \1\.s ++** ret ++*/ ++svbool_t ++test3 () ++{ ++ return svtrn1_b32 (svptrue_b8 (), svptrue_b32 ()); ++} ++ ++/* ++** test4: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** trn1 p0\.s, \1\.s, p[0-3]\.s ++** ret ++*/ ++svbool_t ++test4 () ++{ ++ return svtrn1_b32 (svptrue_b32 (), svptrue_b8 ()); ++} ++ ++/* ++** test5: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** trn1 p0\.d, p[0-3]\.d, \1\.d ++** ret ++*/ ++svbool_t ++test5 () ++{ ++ return svtrn1_b64 (svptrue_b8 (), svptrue_b64 ()); ++} ++ ++/* ++** test6: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** trn1 p0\.d, \1\.d, p[0-3]\.d ++** ret ++*/ ++svbool_t ++test6 () ++{ ++ return svtrn1_b64 (svptrue_b64 (), svptrue_b8 ()); ++} ++ ++#ifdef __cplusplus ++} ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_3.c +@@ -0,0 +1,96 @@ ++/* { dg-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++** test1: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** trn2 p0\.h, p[0-3]\.h, \1\.h ++** ret ++*/ ++svbool_t ++test1 () ++{ ++ return svtrn2_b16 (svptrue_b8 (), svptrue_b16 ()); ++} ++ ++/* ++** test2: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** trn2 p0\.h, \1\.h, p[0-3]\.h ++** ret ++*/ ++svbool_t ++test2 () ++{ ++ return svtrn2_b16 (svptrue_b16 (), svptrue_b8 ()); ++} ++ ++/* ++** test3: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** trn2 p0\.s, p[0-3]\.s, \1\.s ++** ret ++*/ ++svbool_t ++test3 () ++{ ++ return svtrn2_b32 (svptrue_b8 (), svptrue_b32 ()); ++} ++ ++/* ++** test4: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** trn2 p0\.s, \1\.s, p[0-3]\.s ++** ret ++*/ ++svbool_t ++test4 () ++{ ++ return svtrn2_b32 (svptrue_b32 (), svptrue_b8 ()); ++} ++ ++/* ++** test5: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** trn2 p0\.d, p[0-3]\.d, \1\.d ++** ret ++*/ ++svbool_t ++test5 () ++{ ++ return svtrn2_b64 (svptrue_b8 (), svptrue_b64 ()); ++} ++ ++/* ++** test6: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** trn2 p0\.d, \1\.d, p[0-3]\.d ++** ret ++*/ ++svbool_t ++test6 () ++{ ++ return svtrn2_b64 (svptrue_b64 (), svptrue_b8 ()); ++} ++ ++#ifdef __cplusplus ++} ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_4.c +@@ -0,0 +1,96 @@ ++/* { dg-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++** test1: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** zip1 p0\.h, p[0-3]\.h, \1\.h ++** ret ++*/ ++svbool_t ++test1 () ++{ ++ return svzip1_b16 (svptrue_b8 (), svptrue_b16 ()); ++} ++ ++/* ++** test2: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** zip1 p0\.h, \1\.h, p[0-3]\.h ++** ret ++*/ ++svbool_t ++test2 () ++{ ++ return svzip1_b16 (svptrue_b16 (), svptrue_b8 ()); ++} ++ ++/* ++** test3: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** zip1 p0\.s, p[0-3]\.s, \1\.s ++** ret ++*/ ++svbool_t ++test3 () ++{ ++ return svzip1_b32 (svptrue_b8 (), svptrue_b32 ()); ++} ++ ++/* ++** test4: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** zip1 p0\.s, \1\.s, p[0-3]\.s ++** ret ++*/ ++svbool_t ++test4 () ++{ ++ return svzip1_b32 (svptrue_b32 (), svptrue_b8 ()); ++} ++ ++/* ++** test5: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** zip1 p0\.d, p[0-3]\.d, \1\.d ++** ret ++*/ ++svbool_t ++test5 () ++{ ++ return svzip1_b64 (svptrue_b8 (), svptrue_b64 ()); ++} ++ ++/* ++** test6: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** zip1 p0\.d, \1\.d, p[0-3]\.d ++** ret ++*/ ++svbool_t ++test6 () ++{ ++ return svzip1_b64 (svptrue_b64 (), svptrue_b8 ()); ++} ++ ++#ifdef __cplusplus ++} ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_5.c +@@ -0,0 +1,96 @@ ++/* { dg-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++** test1: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** zip2 p0\.h, p[0-3]\.h, \1\.h ++** ret ++*/ ++svbool_t ++test1 () ++{ ++ return svzip2_b16 (svptrue_b8 (), svptrue_b16 ()); ++} ++ ++/* ++** test2: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** zip2 p0\.h, \1\.h, p[0-3]\.h ++** ret ++*/ ++svbool_t ++test2 () ++{ ++ return svzip2_b16 (svptrue_b16 (), svptrue_b8 ()); ++} ++ ++/* ++** test3: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** zip2 p0\.s, p[0-3]\.s, \1\.s ++** ret ++*/ ++svbool_t ++test3 () ++{ ++ return svzip2_b32 (svptrue_b8 (), svptrue_b32 ()); ++} ++ ++/* ++** test4: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** zip2 p0\.s, \1\.s, p[0-3]\.s ++** ret ++*/ ++svbool_t ++test4 () ++{ ++ return svzip2_b32 (svptrue_b32 (), svptrue_b8 ()); ++} ++ ++/* ++** test5: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** zip2 p0\.d, p[0-3]\.d, \1\.d ++** ret ++*/ ++svbool_t ++test5 () ++{ ++ return svzip2_b64 (svptrue_b8 (), svptrue_b64 ()); ++} ++ ++/* ++** test6: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** zip2 p0\.d, \1\.d, p[0-3]\.d ++** ret ++*/ ++svbool_t ++test6 () ++{ ++ return svzip2_b64 (svptrue_b64 (), svptrue_b8 ()); ++} ++ ++#ifdef __cplusplus ++} ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_6.c +@@ -0,0 +1,96 @@ ++/* { dg-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++** test1: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** uzp1 p0\.h, p[0-3]\.h, \1\.h ++** ret ++*/ ++svbool_t ++test1 () ++{ ++ return svuzp1_b16 (svptrue_b8 (), svptrue_b16 ()); ++} ++ ++/* ++** test2: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** uzp1 p0\.h, \1\.h, p[0-3]\.h ++** ret ++*/ ++svbool_t ++test2 () ++{ ++ return svuzp1_b16 (svptrue_b16 (), svptrue_b8 ()); ++} ++ ++/* ++** test3: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** uzp1 p0\.s, p[0-3]\.s, \1\.s ++** ret ++*/ ++svbool_t ++test3 () ++{ ++ return svuzp1_b32 (svptrue_b8 (), svptrue_b32 ()); ++} ++ ++/* ++** test4: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** uzp1 p0\.s, \1\.s, p[0-3]\.s ++** ret ++*/ ++svbool_t ++test4 () ++{ ++ return svuzp1_b32 (svptrue_b32 (), svptrue_b8 ()); ++} ++ ++/* ++** test5: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** uzp1 p0\.d, p[0-3]\.d, \1\.d ++** ret ++*/ ++svbool_t ++test5 () ++{ ++ return svuzp1_b64 (svptrue_b8 (), svptrue_b64 ()); ++} ++ ++/* ++** test6: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** uzp1 p0\.d, \1\.d, p[0-3]\.d ++** ret ++*/ ++svbool_t ++test6 () ++{ ++ return svuzp1_b64 (svptrue_b64 (), svptrue_b8 ()); ++} ++ ++#ifdef __cplusplus ++} ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/perm_7.c +@@ -0,0 +1,96 @@ ++/* { dg-options "-O2" } */ ++/* { dg-final { check-function-bodies "**" "" } } */ ++ ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++** test1: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** uzp2 p0\.h, p[0-3]\.h, \1\.h ++** ret ++*/ ++svbool_t ++test1 () ++{ ++ return svuzp2_b16 (svptrue_b8 (), svptrue_b16 ()); ++} ++ ++/* ++** test2: ++** ... ++** ptrue (p[0-3])\.h, all ++** ... ++** uzp2 p0\.h, \1\.h, p[0-3]\.h ++** ret ++*/ ++svbool_t ++test2 () ++{ ++ return svuzp2_b16 (svptrue_b16 (), svptrue_b8 ()); ++} ++ ++/* ++** test3: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** uzp2 p0\.s, p[0-3]\.s, \1\.s ++** ret ++*/ ++svbool_t ++test3 () ++{ ++ return svuzp2_b32 (svptrue_b8 (), svptrue_b32 ()); ++} ++ ++/* ++** test4: ++** ... ++** ptrue (p[0-3])\.s, all ++** ... ++** uzp2 p0\.s, \1\.s, p[0-3]\.s ++** ret ++*/ ++svbool_t ++test4 () ++{ ++ return svuzp2_b32 (svptrue_b32 (), svptrue_b8 ()); ++} ++ ++/* ++** test5: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** uzp2 p0\.d, p[0-3]\.d, \1\.d ++** ret ++*/ ++svbool_t ++test5 () ++{ ++ return svuzp2_b64 (svptrue_b8 (), svptrue_b64 ()); ++} ++ ++/* ++** test6: ++** ... ++** ptrue (p[0-3])\.d, all ++** ... ++** uzp2 p0\.d, \1\.d, p[0-3]\.d ++** ret ++*/ ++svbool_t ++test6 () ++{ ++ return svuzp2_b64 (svptrue_b64 (), svptrue_b8 ()); ++} ++ ++#ifdef __cplusplus ++} ++#endif +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/pr121118_1.c +@@ -0,0 +1,16 @@ ++/* { dg-options "-O2 -msve-vector-bits=512" } */ ++ ++typedef __SVBool_t fixed_bool __attribute__((arm_sve_vector_bits(512))); ++ ++#define TEST_CONST(NAME, CONST) \ ++ fixed_bool \ ++ NAME () \ ++ { \ ++ union { unsigned long long i; fixed_bool pg; } u = { CONST }; \ ++ return u.pg; \ ++ } ++ ++TEST_CONST (test1, 0x02aaaaaaaa) ++TEST_CONST (test2, 0x0155555557) ++TEST_CONST (test3, 0x0013333333333333ULL) ++TEST_CONST (test4, 0x0011111111111113ULL) +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/aarch64/sve/acle/general/rev_2.c +@@ -0,0 +1,27 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++ ++#include ++ ++svbool_t test1() ++{ ++ return svrev_b16 (svptrue_b16 ()); ++} ++ ++svbool_t test2() ++{ ++ return svrev_b32 (svptrue_b32 ()); ++} ++ ++svbool_t test3() ++{ ++ return svrev_b64 (svptrue_b64 ()); ++} ++ ++/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.h} } } */ ++/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.s} } } */ ++/* { dg-final { scan-assembler {\tptrue\tp[0-7]\.d} } } */ ++/* { dg-final { scan-assembler-not {\tptrue\tp[0-7]\.b} } } */ ++/* { dg-final { scan-assembler {\trev\tp0\.h} } } */ ++/* { dg-final { scan-assembler {\trev\tp0\.s} } } */ ++/* { dg-final { scan-assembler {\trev\tp0\.d} } } */ +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/aarch64/sve/permute_5.c @@ -0,0 +1,10 @@ +/* { dg-options "-O -msve-vector-bits=256" } */ @@ -4492,6 +6198,91 @@ new file mode 100644 +} new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr121208-1a.c +@@ -0,0 +1,15 @@ ++/* { dg-do compile { target *-*-linux* } } */ ++/* { dg-options "-O2 -fPIC -mno-sse -mno-mmx -mno-80387 -mtls-dialect=gnu" } */ ++ ++extern __thread int bar; ++extern void func (void); ++ ++__attribute__((no_caller_saved_registers)) ++void ++foo (int error) ++{ ++ bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ ++ if (error == 0) ++ func (); ++ bar = 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr121208-1b.c +@@ -0,0 +1,4 @@ ++/* { dg-do compile { target *-*-linux* } } */ ++/* { dg-options "-O2 -fPIC -mno-sse -mno-mmx -mno-80387 -mtls-dialect=gnu2" } */ ++ ++#include "pr121208-1a.c" +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr121208-2a.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile { target *-*-linux* } } */ ++/* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */ ++ ++typedef unsigned int uword_t __attribute__ ((mode (__word__))); ++extern __thread int bar; ++extern void func (void); ++ ++__attribute__((target("general-regs-only"))) ++__attribute__((interrupt)) ++void ++foo (void *frame, uword_t error) ++{ ++ bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ ++ if (error == 0) ++ func (); ++ bar = 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr121208-2b.c +@@ -0,0 +1,4 @@ ++/* { dg-do compile { target *-*-linux* } } */ ++/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ ++ ++#include "pr121208-2a.c" +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr121208-3a.c +@@ -0,0 +1,17 @@ ++/* { dg-do compile { target *-*-linux* } } */ ++/* { dg-options "-O2 -fPIC -mtls-dialect=gnu" } */ ++ ++typedef unsigned int uword_t __attribute__ ((mode (__word__))); ++extern __thread int bar; ++extern void func (void); ++ ++__attribute__((target("general-regs-only"))) ++__attribute__((interrupt)) ++void ++foo (void *frame) ++{ ++ bar = 1; /* { dg-error -mtls-dialect=gnu2 } */ ++ if (frame == 0) ++ func (); ++ bar = 0; ++} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/i386/pr121208-3b.c +@@ -0,0 +1,4 @@ ++/* { dg-do compile { target *-*-linux* } } */ ++/* { dg-options "-O2 -fPIC -mtls-dialect=gnu2" } */ ++ ++#include "pr121208-3a.c" +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gcc.target/i386/pr121274.c @@ -0,0 +1,24 @@ +/* { dg-do compile { target { ! ia32 } } } */ @@ -4560,6 +6351,64 @@ new file mode 100644 + if (long_filter_ehigh_3830_1 (buffer, 2) != -1) + __builtin_trap (); +} +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gcc.target/loongarch/pr121542.c +@@ -0,0 +1,54 @@ ++/* { dg-do compile } */ ++/* { dg-options "-mrecip=all -mfrecipe -mabi=lp64d -march=loongarch64 -mfpu=64 -msimd=lasx -Ofast" } */ ++ ++typedef long unsigned int STRLEN; ++typedef struct sv SV; ++struct sv ++{ ++ void *sv_any; ++ unsigned int sv_refcnt; ++ unsigned int sv_flags; ++}; ++typedef struct xpv XPV; ++struct xpv ++{ ++ char *xpv_pv; ++ STRLEN xpv_cur; ++ STRLEN xpv_len; ++}; ++typedef unsigned long UV; ++extern char *PL_bufend; ++extern char *d; ++SV *Perl_newSV (STRLEN len); ++ ++char * ++S_scan_const (char *start) ++{ ++ register char *send = PL_bufend; ++ SV *sv = Perl_newSV (send - start); ++ register char *s = start; ++ UV uv; ++ ++ while (s < send) ++ { ++ if (!(((UV)(uv)) < 0x80)) ++ { ++ int hicount = 0; ++ unsigned char *c; ++ for (c = (unsigned char *)((XPV *)(sv)->sv_any)->xpv_pv; ++ c < (unsigned char *)d; c++) ++ { ++ if (!(((UV)(*c)) < 0x80)) ++ { ++ hicount++; ++ } ++ } ++ d += hicount; ++ *d++ = (char)uv; ++ } ++ ++ s++; ++ } ++ ++ return s; ++} --- a/src/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c +++ b/src/gcc/testsuite/gcc.target/powerpc/builtin_altivec_tr_stxvr_runnable.c @@ -27,10 +27,10 @@ int @@ -5099,6 +6948,107 @@ new file mode 100644 + + deallocate (yourlist) +end program foo +new file mode 100644 +--- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/interface_63.f90 +@@ -0,0 +1,97 @@ ++! { dg-do compile } ++! PR fortran/120784 - fix checking of renamed-on-use interface name ++! ++! Contributed by Matt Thompson ++ ++module A_mod ++ implicit none ++ ++ interface Get ++ procedure :: get_1 ++ procedure :: get_2 ++ end interface Get ++ ++contains ++ ++ subroutine get_1(i) ++ integer :: i ++ i = 5 ++ end subroutine get_1 ++ ++ subroutine get_2(x) ++ real :: x ++ x = 4 ++ end subroutine get_2 ++end module A_mod ++ ++module B_mod ++ use A_mod, only : MyGet => Get ++ implicit none ++ ++ interface MyGet ++ procedure :: other_get ++ end interface MyGet ++ ++contains ++ ++ subroutine other_get(c) ++ character(1) :: c ++ c = 'a' ++ end subroutine other_get ++ ++ subroutine check_get () ++ character :: c ++ integer :: i ++ real :: r ++ call myget (c) ++ call myget (i) ++ call myget (r) ++ end subroutine check_get ++ ++end module B_MOD ++ ++program p ++ use b_mod, only: myget ++ implicit none ++ character :: c ++ integer :: i ++ real :: r ++ call myget (c) ++ call myget (i) ++ call myget (r) ++end ++ ++! Check that we do not regress on the following: ++ ++module mod1 ++ implicit none ++ ++ interface local ++ module procedure local_data ++ end interface local ++ ++contains ++ ++ logical function local_data (data) result (local) ++ real, intent(in) :: data ++ local = .true. ++ end function local_data ++ ++end module mod1 ++ ++module mod2 ++ use mod1, only: local ++ implicit none ++ ++ interface local ++ module procedure local_invt ++ end interface local ++ ++contains ++ ++ logical function local_invt (invt) result (local) ++ integer, intent(in) :: invt ++ local = .true. ++ end function local_invt ++ ++end module mod2 --- a/src/gcc/testsuite/gfortran.dg/pdt_26.f03 +++ b/src/gcc/testsuite/gfortran.dg/pdt_26.f03 @@ -43,4 +43,4 @@ program test_pdt @@ -5109,6 +7059,56 @@ new file mode 100644 +! { dg-final { scan-tree-dump-times "__builtin_malloc" 9 "original" } } new file mode 100644 --- /dev/null ++++ b/src/gcc/testsuite/gfortran.dg/pointer_check_15.f90 +@@ -0,0 +1,46 @@ ++! { dg-do run } ++! { dg-additional-options "-O -fcheck=pointer -fdump-tree-original" } ++! ++! PR fortran/121145 ++! Erroneous runtime error: Proc-pointer actual argument 'ptr' is not associated ++! ++! Contributed by Federico Perini. ++ ++module m ++ implicit none ++ ++ abstract interface ++ subroutine fun(x) ++ real, intent(in) :: x ++ end subroutine fun ++ end interface ++ ++contains ++ ++ subroutine with_fun(sub) ++ procedure(fun), optional :: sub ++ if (present(sub)) stop 1 ++ end subroutine ++ ++ subroutine with_non_optional(sub) ++ procedure(fun) :: sub ++ end subroutine ++ ++end module m ++ ++program p ++ use m ++ implicit none ++ ++ procedure(fun), pointer :: ptr1 => null() ++ procedure(fun), pointer :: ptr2 => null() ++ ++ call with_fun() ++ call with_fun(sub=ptr1) ! no runtime check here ++ ++ if (associated (ptr2)) then ++ call with_non_optional(sub=ptr2) ! runtime check here ++ end if ++end ++ ++! { dg-final { scan-tree-dump-times "Proc-pointer actual argument .'ptr2.'" 1 "original" } } +new file mode 100644 +--- /dev/null +++ b/src/gcc/testsuite/gnat.dg/specs/opt7.ads @@ -0,0 +1,15 @@ +-- { dg-do compile } @@ -5191,6 +7191,57 @@ new file mode 100644 + raise Program_Error; + end if; +end; +--- a/src/gcc/testsuite/lib/multiline.exp ++++ b/src/gcc/testsuite/lib/multiline.exp +@@ -153,6 +153,9 @@ proc handle-multiline-outputs { text } { + # If dg-enable-nn-line-numbers was provided, then obscure source-margin + # line numbers by converting them to "NN" form. + set text [maybe-handle-nn-line-numbers $text] ++ ++ # Remove Windows .exe suffix ++ regsub -all "(as|cc1|cc1plus|collect2|f951|ld|lto-wrapper)\.exe?:" $text {\1:} text + + set index 0 + foreach entry $multiline_expected_outputs { +--- a/src/gcc/testsuite/lib/target-supports.exp ++++ b/src/gcc/testsuite/lib/target-supports.exp +@@ -5388,6 +5388,13 @@ proc add_options_for_aarch64_sve { flags } { + return "$flags -march=armv8.2-a+sve" + } + ++proc add_options_for_aarch64_sme { flags } { ++ if { ![istarget aarch64*-*-*] || [check_effective_target_aarch64_sme] } { ++ return "$flags" ++ } ++ return "$flags -march=armv9-a+sme" ++} ++ + # Return 1 if this is an ARM target supporting the FP16 alternative + # format. Some multilibs may be incompatible with the options needed. Also + # set et_arm_fp16_alternative_flags to the best options to add. +@@ -6037,6 +6044,22 @@ foreach N { 128 256 512 1024 2048 } { + }] + } + ++# Return true if this is an AArch64 target that can run SME code. ++ ++proc check_effective_target_aarch64_sme_hw { } { ++ if { ![istarget aarch64*-*-*] } { ++ return 0 ++ } ++ return [check_runtime aarch64_sme_hw_available { ++ int ++ main (void) ++ { ++ asm volatile ("rdsvl x0, #1"); ++ return 0; ++ } ++ } [add_options_for_aarch64_sme ""]] ++} ++ + proc check_effective_target_arm_neonv2_hw { } { + return [check_runtime arm_neon_hwv2_available { + #include "arm_neon.h" --- a/src/gcc/tree-chrec.cc +++ b/src/gcc/tree-chrec.cc @@ -1490,7 +1490,7 @@ convert_affine_scev (class loop *loop, tree type, @@ -5202,6 +7253,51 @@ new file mode 100644 new_step = chrec_convert (signed_ct, new_step, at_stmt, use_overflow_semantics); } +--- a/src/gcc/tree-sra.cc ++++ b/src/gcc/tree-sra.cc +@@ -2480,6 +2480,12 @@ sort_and_splice_var_accesses (tree var) + } + unscalarizable_region = true; + } ++ /* If there the same place is accessed with two incompatible ++ aggregate types, trying to base total scalarization on either of ++ them can be wrong. */ ++ if (!first_scalar && !types_compatible_p (access->type, ac2->type)) ++ bitmap_set_bit (cannot_scalarize_away_bitmap, ++ DECL_UID (access->base)); + + if (grp_same_access_path + && (!ac2->grp_same_access_path +@@ -2865,7 +2871,10 @@ analyze_access_subtree (struct access *root, struct access *parent, + + for (child = root->first_child; child; child = child->next_sibling) + { +- hole |= covered_to < child->offset; ++ if (totally) ++ covered_to = child->offset; ++ else ++ hole |= covered_to < child->offset; + sth_created |= analyze_access_subtree (child, root, + allow_replacements && !scalar + && !root->grp_partial_lhs, +@@ -2876,6 +2885,8 @@ analyze_access_subtree (struct access *root, struct access *parent, + covered_to += child->size; + else + hole = true; ++ if (totally && !hole) ++ covered_to = limit; + } + + if (allow_replacements && scalar && !root->first_child +@@ -2948,7 +2959,7 @@ analyze_access_subtree (struct access *root, struct access *parent, + root->grp_total_scalarization = 0; + } + +- if (!hole || totally) ++ if (!hole) + root->grp_covered = 1; + else if (root->grp_write || comes_initialized_p (root->base)) + root->grp_unscalarized_data = 1; /* not covered and written to */ --- a/src/gcc/tree-ssa-math-opts.cc +++ b/src/gcc/tree-ssa-math-opts.cc @@ -1052,6 +1052,7 @@ pass_cse_reciprocals::execute (function *fun) @@ -5277,6 +7373,178 @@ new file mode 100644 *code1 = as_combined_fn (lo); *code2 = as_combined_fn (hi); optab1 = direct_internal_fn_optab (lo, {vectype, vectype}); +--- a/src/libgcc/ChangeLog ++++ b/src/libgcc/ChangeLog +@@ -1,3 +1,13 @@ ++2025-08-15 Richard Sandiford ++ ++ Backported from master: ++ 2025-07-17 Richard Sandiford ++ Yury Khrustalev ++ ++ * config/aarch64/linux-unwind.h (aarch64_fallback_frame_state): ++ If a signal was raised while there was an uncommitted lazy save, ++ commit the save as part of the unwind process. ++ + 2025-05-23 Release Manager + + * GCC 14.3.0 released. +--- a/src/libgcc/config/aarch64/linux-unwind.h ++++ b/src/libgcc/config/aarch64/linux-unwind.h +@@ -27,7 +27,7 @@ + + #include + #include +- ++#include + + /* Since insns are always stored LE, on a BE system the opcodes will + be loaded byte-reversed. Therefore, define two sets of opcodes, +@@ -43,6 +43,22 @@ + + #define MD_FALLBACK_FRAME_STATE_FOR aarch64_fallback_frame_state + ++#ifndef FPSIMD_MAGIC ++#define FPSIMD_MAGIC 0x46508001 ++#endif ++ ++#ifndef TPIDR2_MAGIC ++#define TPIDR2_MAGIC 0x54504902 ++#endif ++ ++#ifndef ZA_MAGIC ++#define ZA_MAGIC 0x54366345 ++#endif ++ ++#ifndef EXTRA_MAGIC ++#define EXTRA_MAGIC 0x45585401 ++#endif ++ + static _Unwind_Reason_Code + aarch64_fallback_frame_state (struct _Unwind_Context *context, + _Unwind_FrameState * fs) +@@ -58,6 +74,21 @@ aarch64_fallback_frame_state (struct _Unwind_Context *context, + ucontext_t uc; + }; + ++ struct tpidr2_block ++ { ++ uint64_t za_save_buffer; ++ uint16_t num_za_save_slices; ++ uint8_t reserved[6]; ++ }; ++ ++ struct za_block ++ { ++ struct _aarch64_ctx head; ++ uint16_t vl; ++ uint16_t reserved[3]; ++ uint64_t data; ++ }; ++ + struct rt_sigframe *rt_; + _Unwind_Ptr new_cfa; + unsigned *pc = context->ra; +@@ -103,11 +134,15 @@ aarch64_fallback_frame_state (struct _Unwind_Context *context, + field can be used to skip over unrecognized context extensions. + The end of the context sequence is marked by a context with magic + 0 or size 0. */ ++ struct tpidr2_block *tpidr2 = 0; ++ struct za_block *za_ctx = 0; ++ + for (extension_marker = (struct _aarch64_ctx *) &sc->__reserved; + extension_marker->magic; + extension_marker = (struct _aarch64_ctx *) + ((unsigned char *) extension_marker + extension_marker->size)) + { ++ restart: + if (extension_marker->magic == FPSIMD_MAGIC) + { + struct fpsimd_context *ctx = +@@ -139,12 +174,83 @@ aarch64_fallback_frame_state (struct _Unwind_Context *context, + fs->regs.reg[AARCH64_DWARF_V0 + i].loc.offset = offset; + } + } ++ else if (extension_marker->magic == TPIDR2_MAGIC) ++ { ++ /* A TPIDR2 context. ++ ++ All the casting is to support big-endian ILP32. We could read ++ directly into TPIDR2 otherwise. */ ++ struct { struct _aarch64_ctx h; uint64_t tpidr2; } *ctx ++ = (void *)extension_marker; ++#if defined (__ILP32__) ++ tpidr2 = (struct tpidr2_block *) (uintptr_t) ctx->tpidr2; ++#else ++ tpidr2 = (struct tpidr2_block *) ctx->tpidr2; ++#endif ++ } ++ else if (extension_marker->magic == ZA_MAGIC) ++ /* A ZA context. We interpret this later. */ ++ za_ctx = (void *)extension_marker; ++ else if (extension_marker->magic == EXTRA_MAGIC) ++ { ++ /* Extra context. The ABI guarantees that the next _aarch64_ctx ++ in the current list will be the zero terminator, so we can simply ++ switch to the new list and continue from there. The new list is ++ also zero-terminated. ++ ++ As above, the casting is to support big-endian ILP32. */ ++ struct { struct _aarch64_ctx h; uint64_t next; } *ctx ++ = (void *)extension_marker; ++#if defined (__ILP32__) ++ extension_marker = (struct _aarch64_ctx *) (uintptr_t) ctx->next; ++#else ++ extension_marker = (struct _aarch64_ctx *) ctx->next; ++#endif ++ goto restart; ++ } + else + { + /* There is context provided that we do not recognize! */ + } + } + ++ /* Signal handlers are entered with ZA in the off state (TPIDR2_ELO==0 and ++ PSTATE.ZA==0). The normal process when transitioning from ZA being ++ dormant to ZA being off is to commit the lazy save; see the AAPCS64 ++ for details. However, this is not done when entering a signal handler. ++ Instead, linux saves the old contents of ZA and TPIDR2_EL0 to the ++ sigcontext without interpreting them further. ++ ++ Therefore, if a signal handler throws an exception to code outside the ++ signal handler, the unwinder must commit the lazy save after the fact. ++ Committing a lazy save means: ++ ++ (1) Storing the contents of ZA into the buffer provided by TPIDR2_EL0. ++ (2) Setting TPIDR2_EL0 to zero. ++ (3) Turning ZA off. ++ ++ (2) and (3) have already been done by the call to __libgcc_arm_za_disable. ++ (1) involves copying data from the ZA sigcontext entry to the ++ corresponding lazy save buffer. */ ++ if (tpidr2 && za_ctx && tpidr2->za_save_buffer) ++ { ++ /* There is a 16-bit vector length (measured in bytes) at ZA_CTX + 8. ++ The data itself starts at ZA_CTX + 16. ++ As above, the casting is to support big-endian ILP32. */ ++ uint16_t vl = za_ctx->vl; ++#if defined (__ILP32__) ++ void *save_buffer = (void *) (uintptr_t) tpidr2->za_save_buffer; ++ const void *za_buffer = (void *) (uintptr_t) &za_ctx->data; ++#else ++ void *save_buffer = (void *) tpidr2->za_save_buffer; ++ const void *za_buffer = (void *) &za_ctx->data; ++#endif ++ uint64_t num_slices = tpidr2->num_za_save_slices; ++ if (num_slices > vl) ++ num_slices = vl; ++ memcpy (save_buffer, za_buffer, num_slices * vl); ++ } ++ + fs->regs.how[31] = REG_SAVED_OFFSET; + fs->regs.reg[31].loc.offset = (_Unwind_Ptr) & (sc->sp) - new_cfa; + --- a/src/libgcc/config/avr/libf7/ChangeLog +++ b/src/libgcc/config/avr/libf7/ChangeLog @@ -1,3 +1,11 @@ diff --git a/debian/patches/libphobos-ppc64el.diff b/debian/patches/libphobos-ppc64el.diff new file mode 100644 index 0000000..8fe038e --- /dev/null +++ b/debian/patches/libphobos-ppc64el.diff @@ -0,0 +1,20 @@ +# DP: build libphobos on ppc64el when configured --with-long-double-format=ieee + +--- a/src/libphobos/configure.tgt ++++ b/src/libphobos/configure.tgt +@@ -48,6 +48,15 @@ + power*-*-freebsd*) + LIBPHOBOS_SUPPORTED=yes + ;; ++ powerpc64le-*-linux*) ++ LIBPHOBOS_SUPPORTED=yes ++ case "$ac_configure_args" in ++ *--with-long-double-format=ieee*) ++ ;; ++ *) ++ LIBDRUNTIME_ONLY=yes ++ esac ++ ;; + power*-*-linux*) + LIBPHOBOS_SUPPORTED=yes + LIBDRUNTIME_ONLY=yes diff --git a/debian/patches/libphobos-sparc64.diff b/debian/patches/libphobos-sparc64.diff new file mode 100644 index 0000000..a725338 --- /dev/null +++ b/debian/patches/libphobos-sparc64.diff @@ -0,0 +1,12 @@ +--- a/src/libphobos/configure.tgt ++++ b/src/libphobos/configure.tgt +@@ -61,6 +61,9 @@ case "${target}" in + s390*-linux*) + LIBPHOBOS_SUPPORTED=yes + ;; ++ sparc64-*-linux*) ++ LIBPHOBOS_SUPPORTED=yes ++ ;; + x86_64-*-freebsd* | i?86-*-freebsd*) + LIBPHOBOS_SUPPORTED=yes + ;; diff --git a/debian/patches/newlib-p2.diff b/debian/patches/newlib-p2.diff new file mode 100644 index 0000000..5b885f3 --- /dev/null +++ b/debian/patches/newlib-p2.diff @@ -0,0 +1,23 @@ +commit f13e8e21599ff12ea76980d6a8b19b0a5ebe9bed +Author: Andrew Stubbs +Date: Thu Aug 7 13:09:41 2025 +0000 + + amdgcn, libm: fix infinite loop + + +--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c +@@ -70,8 +70,11 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y) + v64si iy; + VECTOR_IF (hy < 0x00800000, cond) // subnormal y + iy = VECTOR_INIT (-126); +- for (v64si i = (hy << 8); !ALL_ZEROES_P (cond & (i >= 0)); i <<= 1) +- VECTOR_COND_MOVE (iy, iy - 1, cond & (i >= 0)); ++ for (v64si i = (hy << 8); !ALL_ZEROES_P (cond & (i >= 0)); /* i <<= 1 */) ++ { ++ VECTOR_COND_MOVE (iy, iy - 1, cond & (i >= 0)); ++ VECTOR_COND_MOVE (i, i << 1, cond & (i >= 0)); ++ } + VECTOR_ELSE (cond) + VECTOR_COND_MOVE (iy, (hy >> 23) - 127, cond); + VECTOR_ENDIF diff --git a/debian/patches/newlib-p3.diff b/debian/patches/newlib-p3.diff new file mode 100644 index 0000000..d133d9e --- /dev/null +++ b/debian/patches/newlib-p3.diff @@ -0,0 +1,301 @@ +commit bd409f3c12e28e1464dec7fd0d45db30280f1e56 +Author: Andrew Stubbs +Date: Wed Aug 27 10:11:25 2025 +0000 + + amdgcn, libm: fix vector ilogb bugs (bug 33272) + + +--- a/newlib/libm/machine/amdgcn/amdgcn_veclib.h ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/amdgcn_veclib.h +@@ -267,7 +267,15 @@ do { \ + __tmp; \ + }) + +-#define VECTOR_WHILE(cond, cond_var, prev_cond_var) \ ++#define VECTOR_WHILE(cond, cond_var) \ ++{ \ ++ __auto_type cond_var = __mask; \ ++ for (;;) { \ ++ cond_var &= __builtin_convertvector (cond, __typeof (cond_var)); \ ++ if (ALL_ZEROES_P (cond_var)) \ ++ break; ++ ++#define VECTOR_WHILE2(cond, cond_var, prev_cond_var) \ + { \ + __auto_type cond_var = prev_cond_var; \ + for (;;) { \ +--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_fmod.c ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_fmod.c +@@ -61,17 +61,19 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y) + v64si ix; + VECTOR_IF (hx < 0x00100000, cond) // subnormal x + VECTOR_IF2 (hx == 0, cond2, cond) +- ix = VECTOR_INIT (-1043); +- for (v64si i = __builtin_convertvector (lx, v64si); +- !ALL_ZEROES_P (cond2 & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0)); ++ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1043), cond2); ++ v64si i = __builtin_convertvector (lx, v64si); ++ VECTOR_WHILE2 (i > 0, cond3, cond2); ++ VECTOR_COND_MOVE (ix, ix - 1, cond3); ++ VECTOR_COND_MOVE (i, i << 1, cond3); ++ VECTOR_ENDWHILE + VECTOR_ELSE2 (cond2, cond) +- ix = VECTOR_INIT (-1022); +- for (v64si i = __builtin_convertvector (hx << 11, v64si); +- !ALL_ZEROES_P (cond2 & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0)); ++ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1022), cond2); ++ v64si i = __builtin_convertvector (hx << 11, v64si); ++ VECTOR_WHILE2 (i > 0, cond3, cond2) ++ VECTOR_COND_MOVE (ix, ix - 1, cond3); ++ VECTOR_COND_MOVE (i, i << 1, cond3); ++ VECTOR_ENDWHILE + VECTOR_ENDIF + VECTOR_ELSE (cond) + VECTOR_COND_MOVE (ix, (hx >> 20) - 1023, cond); +@@ -81,17 +83,19 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y) + v64si iy; + VECTOR_IF (hy < 0x00100000, cond) // subnormal y + VECTOR_IF2 (hy == 0, cond2, cond) +- iy = VECTOR_INIT (-1043); +- for (v64si i = __builtin_convertvector (ly, v64si); +- !ALL_ZEROES_P (cond2 & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (iy, iy - 1, cond2 & (i > 0)); ++ VECTOR_COND_MOVE (iy, VECTOR_INIT (-1043), cond2); ++ v64si i = __builtin_convertvector (ly, v64si); ++ VECTOR_WHILE2 (i > 0, cond3, cond2); ++ VECTOR_COND_MOVE (iy, iy - 1, cond3); ++ VECTOR_COND_MOVE (i, i << 1, cond3); ++ VECTOR_ENDWHILE + VECTOR_ELSE2 (cond2, cond) +- iy = VECTOR_INIT (-1022); +- for (v64si i = __builtin_convertvector (hy << 11, v64si); +- !ALL_ZEROES_P (cond2 & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (iy, iy - 1, cond2 & (i > 0)); ++ VECTOR_COND_MOVE (iy, VECTOR_INIT (-1022), cond2); ++ v64si i = __builtin_convertvector (hy << 11, v64si); ++ VECTOR_WHILE2 (i > 0, cond3, cond2); ++ VECTOR_COND_MOVE (iy, iy - 1, cond3); ++ VECTOR_COND_MOVE (i, i << 1, cond3); ++ VECTOR_ENDWHILE + VECTOR_ENDIF + VECTOR_ELSE (cond) + VECTOR_COND_MOVE (iy, (hy >> 20) - 1023, cond); +@@ -130,29 +134,26 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y) + + /* fix point fmod */ + v64si n = ix - iy; +- v64si cond = n != 0; + +- while (!ALL_ZEROES_P (cond)) +- { +- hz = hx - hy; +- lz = lx - ly; +- VECTOR_IF2 (lx < ly, cond2, cond) +- VECTOR_COND_MOVE (hz, hz - 1, cond2); +- VECTOR_ENDIF +- VECTOR_IF2 (hz < 0, cond2, cond) +- VECTOR_COND_MOVE (hx, hx + hx + (__builtin_convertvector(lx, v64usi) >> 31), cond2); +- VECTOR_COND_MOVE (lx, lx + lx, cond2); +- VECTOR_ELSE2 (cond2, cond) +- VECTOR_IF2 ((hz | lz) == 0, cond3, cond2) // return sign(x)*0 +- VECTOR_RETURN (zeroes, cond3); +- VECTOR_ENDIF +- VECTOR_COND_MOVE (hx, hz + hz + (__builtin_convertvector(lz, v64usi) >> 31), cond2); +- VECTOR_COND_MOVE (lx, lz + lz, cond2); ++ VECTOR_WHILE (n != 0, cond) ++ hz = hx - hy; ++ lz = lx - ly; ++ VECTOR_IF2 (lx < ly, cond2, cond) ++ VECTOR_COND_MOVE (hz, hz - 1, cond2); ++ VECTOR_ENDIF ++ VECTOR_IF2 (hz < 0, cond2, cond) ++ VECTOR_COND_MOVE (hx, hx + hx + (__builtin_convertvector(lx, v64usi) >> 31), cond2); ++ VECTOR_COND_MOVE (lx, lx + lx, cond2); ++ VECTOR_ELSE2 (cond2, cond) ++ VECTOR_IF2 ((hz | lz) == 0, cond3, cond2) // return sign(x)*0 ++ VECTOR_RETURN (zeroes, cond3); + VECTOR_ENDIF ++ VECTOR_COND_MOVE (hx, hz + hz + (__builtin_convertvector(lz, v64usi) >> 31), cond2); ++ VECTOR_COND_MOVE (lx, lz + lz, cond2); ++ VECTOR_ENDIF + +- n += cond; // Active lanes should be -1 +- cond &= (n != 0); +- } ++ VECTOR_COND_MOVE (n, n - 1, cond); ++ VECTOR_ENDWHILE + + hz = hx - hy; + lz = lx - ly; +@@ -164,15 +165,11 @@ DEF_VD_MATH_FUNC (v64df, fmod, v64df x, v64df y) + + /* convert back to floating value and restore the sign */ + VECTOR_RETURN (zeroes, (hx | lx) == 0); // return sign(x)*0 +- cond = hx < 0x00100000; +- while (!ALL_ZEROES_P (cond)) // normalize x +- { +- VECTOR_COND_MOVE (hx, hx + hx + (lx >> 31), cond); +- VECTOR_COND_MOVE (lx, lx + lx, cond); +- iy += cond; // Active lanes should be -1 +- +- cond &= (hx < 0x00100000); +- } ++ VECTOR_WHILE (hx < 0x00100000, cond) // normalize x ++ VECTOR_COND_MOVE (hx, hx + hx + (lx >> 31), cond); ++ VECTOR_COND_MOVE (lx, lx + lx, cond); ++ VECTOR_COND_MOVE (iy, iy - 1, cond); ++ VECTOR_ENDWHILE + VECTOR_IF (iy >= -1022, cond) // normalize output + VECTOR_COND_MOVE (hx, (hx - 0x00100000) | ((iy + 1023) << 20), cond); + INSERT_WORDS (x, hx | sx, lx, cond); +--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_ilogb.c ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64df_ilogb.c +@@ -36,17 +36,19 @@ DEF_VD_MATH_PRED (v64si, ilogb, v64df x) + VECTOR_IF (hx < 0x00100000, cond) + VECTOR_RETURN (VECTOR_INIT (-__INT_MAX__), cond & ((hx | lx) == 0)); // FP_ILOGB0 + VECTOR_IF2 (hx == 0, cond2, cond) +- ix = VECTOR_INIT (-1043); +- for (v64si i = lx; +- !ALL_ZEROES_P (cond2 & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0)); ++ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1043), cond2); ++ v64si i = lx; ++ VECTOR_WHILE2 (i > 0, cond3, cond2) ++ VECTOR_COND_MOVE (ix, ix - 1, cond3); ++ VECTOR_COND_MOVE (i, i << 1, cond3); ++ VECTOR_ENDWHILE + VECTOR_ELSE2 (cond2, cond) +- ix = VECTOR_INIT (-1022); +- for (v64si i = (hx << 11); +- !ALL_ZEROES_P (cond2 & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (ix, ix - 1, cond2 & (i > 0)); ++ VECTOR_COND_MOVE (ix, VECTOR_INIT (-1022), cond2); ++ v64si i = (hx << 11); ++ VECTOR_WHILE2 (i > 0, cond3, cond2) ++ VECTOR_COND_MOVE (ix, ix - 1, cond3); ++ VECTOR_COND_MOVE (i, i << 1, cond3); ++ VECTOR_ENDWHILE + VECTOR_ENDIF + VECTOR_RETURN (ix, cond); + VECTOR_ENDIF +--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_fmod.c +@@ -57,11 +57,12 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y) + /* determine ix = ilogb(x) */ + v64si ix; + VECTOR_IF (hx < 0x00800000, cond) // subnormal x +- ix = VECTOR_INIT (-126); +- for (v64si i = (hx << 8); +- !ALL_ZEROES_P (cond & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (ix, ix - 1, cond & (i > 0)); ++ VECTOR_COND_MOVE (ix, VECTOR_INIT (-126), cond); ++ v64si i = hx << 8; ++ VECTOR_WHILE2 (i > 0, cond2, cond) ++ VECTOR_COND_MOVE (ix, ix - 1, cond2); ++ VECTOR_COND_MOVE (i, i << 1, cond2); ++ VECTOR_ENDWHILE + VECTOR_ELSE (cond) + VECTOR_COND_MOVE (ix, (hx >> 23) - 127, cond); + VECTOR_ENDIF +@@ -69,12 +70,12 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y) + /* determine iy = ilogb(y) */ + v64si iy; + VECTOR_IF (hy < 0x00800000, cond) // subnormal y +- iy = VECTOR_INIT (-126); +- for (v64si i = (hy << 8); !ALL_ZEROES_P (cond & (i >= 0)); /* i <<= 1 */) +- { +- VECTOR_COND_MOVE (iy, iy - 1, cond & (i >= 0)); +- VECTOR_COND_MOVE (i, i << 1, cond & (i >= 0)); +- } ++ VECTOR_COND_MOVE (iy, VECTOR_INIT (-126), cond); ++ v64si i = (hy << 8); ++ VECTOR_WHILE2 (i >= 0, cond2, cond) ++ VECTOR_COND_MOVE (iy, iy - 1, cond2); ++ VECTOR_COND_MOVE (i, i << 1, cond2); ++ VECTOR_ENDWHILE + VECTOR_ELSE (cond) + VECTOR_COND_MOVE (iy, (hy >> 23) - 127, cond); + VECTOR_ENDIF +@@ -99,24 +100,21 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y) + + /* fix point fmod */ + v64si n = ix - iy; +- v64si cond = n != 0; + +- while (!ALL_ZEROES_P (cond)) +- { +- hz = hx - hy; +- VECTOR_IF2 (hz < 0, cond2, cond) +- VECTOR_COND_MOVE (hx, hx + hx, cond2); +- VECTOR_ELSE2 (cond2, cond) +- VECTOR_IF2 (hz == 0, cond3, cond2) // return sign(x)*0 +- VECTOR_RETURN (zeroes, cond3); +- VECTOR_ELSE2 (cond3, cond2) +- VECTOR_COND_MOVE (hx, hz + hz, cond2); +- VECTOR_ENDIF ++ VECTOR_WHILE (n != 0, cond) ++ hz = hx - hy; ++ VECTOR_IF2 (hz < 0, cond2, cond) ++ VECTOR_COND_MOVE (hx, hx + hx, cond2); ++ VECTOR_ELSE2 (cond2, cond) ++ VECTOR_IF2 (hz == 0, cond3, cond2) // return sign(x)*0 ++ VECTOR_RETURN (zeroes, cond3); ++ VECTOR_ELSE2 (cond3, cond2) ++ VECTOR_COND_MOVE (hx, hz + hz, cond2); + VECTOR_ENDIF ++ VECTOR_ENDIF + +- n += cond; // Active lanes should be -1 +- cond &= (n != 0); +- } ++ n += cond; // Active lanes should be -1 ++ VECTOR_ENDWHILE + + hz = hx - hy; + VECTOR_COND_MOVE (hx, hz, hz >= 0); +@@ -124,14 +122,10 @@ DEF_VS_MATH_FUNC (v64sf, fmodf, v64sf x, v64sf y) + /* convert back to floating value and restore the sign */ + VECTOR_RETURN (zeroes, hx == 0); // return sign(x)*0 + +- cond = hx < 0x00800000; +- while (!ALL_ZEROES_P (cond)) // normalize x +- { ++ VECTOR_WHILE (hx < 0x00800000, cond) // normalize x + VECTOR_COND_MOVE (hx, hx + hx, cond); + iy += cond; // Active lanes should be -1 +- +- cond &= (hx < 0x00800000); +- } ++ VECTOR_ENDWHILE + VECTOR_IF (iy >= -126, cond) // normalize output + VECTOR_COND_MOVE (hx, (hx - 0x00800000) | ((iy + 127) << 23), cond); + SET_FLOAT_WORD (x, hx | sx, cond); +--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_ilogb.c ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/v64sf_ilogb.c +@@ -38,11 +38,12 @@ DEF_VS_MATH_FUNC (v64si, ilogbf, v64sf x) + VECTOR_RETURN (VECTOR_INIT (-__INT_MAX__), cond); // FP_ILOGB0 + VECTOR_ENDIF + VECTOR_IF (FLT_UWORD_IS_SUBNORMAL (hx), cond) +- ix = VECTOR_INIT (-126); +- for (v64si i = (hx << 8); +- !ALL_ZEROES_P (cond & (i > 0)); +- i <<= 1) +- VECTOR_COND_MOVE (ix, ix - 1, cond & (i > 0)); ++ VECTOR_COND_MOVE (ix, VECTOR_INIT (-126), cond); ++ v64si i = (hx << 8); ++ VECTOR_WHILE2 (i > 0, cond2, cond) ++ VECTOR_COND_MOVE (ix, ix - 1, cond2); ++ VECTOR_COND_MOVE (i, i << 1, cond2); ++ VECTOR_ENDWHILE + VECTOR_RETURN (ix, cond); + VECTOR_ELSEIF (~FLT_UWORD_IS_FINITE (hx), cond) + VECTOR_RETURN (VECTOR_INIT (__INT_MAX__), cond); diff --git a/debian/patches/newlib-pr119325.diff b/debian/patches/newlib-pr119325.diff new file mode 100644 index 0000000..9b6f8e1 --- /dev/null +++ b/debian/patches/newlib-pr119325.diff @@ -0,0 +1,43 @@ +From 2ef1a37e7823b21eda524972c006e0e8c26f97b3 Mon Sep 17 00:00:00 2001 +From: Andrew Stubbs +Date: Thu, 20 Mar 2025 09:32:31 +0000 +Subject: [PATCH] Fix GCN SIMD libm bug + +Since January, GCC has been miscompiling Newlib libm on AMD GCN due to +undefined behaviour in the RESIZE_VECTOR macro. It was "working" but expanding +the size of a vector would no longer zero the additional lanes, as it expected. + +See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=119325 +--- + newlib/libm/machine/amdgcn/amdgcn_veclib.h | 17 +++++++++++++++-- + 1 file changed, 15 insertions(+), 2 deletions(-) + +--- a/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/amdgcn_veclib.h ++++ b/newlib-4.5.0.20241231/newlib/libm/machine/amdgcn/amdgcn_veclib.h +@@ -85,8 +85,21 @@ typedef union { + + #define RESIZE_VECTOR(to_t, from) \ + ({ \ +- __auto_type __from = (from); \ +- *((to_t *) &__from); \ ++ to_t __to; \ ++ if (VECTOR_WIDTH (to_t) < VECTOR_WIDTH (__typeof (from))) \ ++ asm ("; no-op cast %0" : "=v"(__to) : "0"(from)); \ ++ else \ ++ { \ ++ unsigned long __mask = -1L; \ ++ int lanes = VECTOR_WIDTH (__typeof (from)); \ ++ __mask <<= lanes; \ ++ __builtin_choose_expr ( \ ++ V_SF_SI_P (to_t), \ ++ ({asm ("v_mov_b32 %0, 0" : "=v"(__to) : "0"(from), "e"(__mask));}), \ ++ ({asm ("v_mov_b32 %H0, 0\n\t" \ ++ "v_mov_b32 %L0, 0" : "=v"(__to) : "0"(from), "e"(__mask));})); \ ++ } \ ++ __to; \ + }) + + /* Bit-wise cast vector FROM to type TO_T. */ +-- +2.43.5 + diff --git a/debian/rules.conf b/debian/rules.conf index 63bd269..ba72595 100644 --- a/debian/rules.conf +++ b/debian/rules.conf @@ -202,8 +202,10 @@ else BINUTILSBDV = 2.36 else ifneq (,$(filter $(distrelease),jammy)) BINUTILSBDV = 2.38 - else + else ifneq (,$(filter $(distrelease),$(no_sframe_distreleases))) BINUTILSBDV = 2.39 + else + BINUTILSBDV = 2.45 endif endif ifeq ($(DEB_CROSS),yes) @@ -539,6 +541,9 @@ else ifneq (,$(filter $(distrelease), bullseye hirsute jammy)) else ifneq (,$(filter $(distrelease), impish)) gnat_build_dep := gnat-11$(NT) [$(ada_no_archs)], g++-11$(NT) gdc_build_dep := gdc-11$(NT) [$(d_no_archs)] +else ifneq (,$(filter $(distrelease), forky questing)) + gnat_build_dep := gnat-13$(NT) [$(ada_no_archs)], g++-13$(NT) + gdc_build_dep := gdc-13$(NT) [$(d_no_archs)] else ifneq (,$(filter $(distrelease), trixie forky)) # FIXME: bump to 14 on all archs before release gnat_build_dep := gnat-14$(NT) [$(ada_no_archs) !m68k], g++-14$(NT) [!m68k], gnat-13$(NT) [m68k], g++-13$(NT) [m68k] diff --git a/debian/rules.defs b/debian/rules.defs index 61b6162..d375425 100644 --- a/debian/rules.defs +++ b/debian/rules.defs @@ -386,6 +386,10 @@ ifneq ($(trunk_build),yes) ifneq (,$(filter $(DEB_HOST_ARCH), alpha hppa ia64 m68k mips mipsel mips64el sh4 sparc64 hurd-amd64 hurd-i386)) with_lto_build := endif + # Slow builders in Debian + ifeq ($(distribution)-$(DEB_HOST_ARCH),Debian-riscv64) + with_lto_build := + endif # FIXME: newer binutils needed? ifneq (,$(filter $(distrelease),stretch precise trusty xenial bionic focal)) @@ -556,6 +560,20 @@ else ifneq (,$(filter $(DEB_TARGET_ARCH), arm armel)) float_abi := soft endif +sframe_archs = amd64 arm64 +no_sframe_distreleases = jessy stretch buster bullseye bookworm trixie \ + forky \ + precise trusty xenial bionic focal jammy kinetic lunar mantic \ + noble oracular plucky questing +ifneq (,$(filter $(DEB_TARGET_ARCH), $(sframe_archs))) + ifeq (,$(filter $(distrelease),$(no_sframe_distreleases))) + with_sframe = yes + endif +endif + +ppc64el_ibm128_distreleases = jessie stretch buster bullseye bookworm trixie \ + precise xenial bionic focal jammy noble oracular plucky + # ------------------------------------------------------------------- # basic config @@ -1046,7 +1064,7 @@ endif # D --------------------------- d_no_cross := yes d_no_snap := -d_no_cpus := alpha arc ia64 m68k sh4 s390 sparc64 +d_no_cpus := alpha arc ia64 m68k sh4 s390 d_no_systems := gnu ifneq ($(separate_lang),yes) @@ -1076,14 +1094,21 @@ ifeq ($(with_base_only),yes) endif ifeq ($(with_d),yes) - druntime_only_archs = powerpc ppc64 ppc64el - phobos_archs = amd64 arm64 armel armhf i386 x32 + phobos_archs = + druntime_only_archs = powerpc ppc64 + ifneq (,$(filter $(distrelease),$(ppc64el_ibm128_distreleases))) + druntime_only_archs += ppc64el + else + phobos_archs += ppc64el + endif + phobos_archs += amd64 arm64 armel armhf i386 x32 phobos_archs += hppa phobos_archs += mips mips64 mipsel mips64el phobos_archs += mipsn32 mipsn32el phobos_archs += mipsr6 mipsr6el mipsn32r6 mipsn32r6el mips64r6 mips64r6el - phobos_archs += riscv64 s390x loong64 + phobos_archs += riscv64 s390x loong64 sparc64 phobos_archs += $(druntime_only_archs) + phobos_archs := $(sort $(phobos_archs)) ifneq (,$(filter $(DEB_TARGET_ARCH), $(phobos_archs))) with_phobos := yes endif diff --git a/debian/rules.patch b/debian/rules.patch index ece61bc..717369e 100644 --- a/debian/rules.patch +++ b/debian/rules.patch @@ -77,6 +77,8 @@ debian_patches += \ libphobos-unittest \ pr118045 \ binutils-pr32491 \ + libphobos-ppc64el \ + libphobos-sparc64 \ # see https://bugs.debian.org/1108322 ifneq (,$(filter $(DEB_TARGET_ARCH),hppa m68k powerpc)) @@ -370,6 +372,10 @@ endif ifeq ($(with_timet64),yes) echo '#define DIST_DEFAULT_TIMET64 1' \ >> $(srcdir)/gcc/distro-defaults.h +endif +ifeq ($(with_sframe),yes) + echo '#define DIST_DEFAULT_SFRAME 1' \ + >> $(srcdir)/gcc/distro-defaults.h endif echo '#endif' \ >> $(srcdir)/gcc/distro-defaults.h diff --git a/debian/rules.unpack b/debian/rules.unpack index 48f0221..536c2b7 100644 --- a/debian/rules.unpack +++ b/debian/rules.unpack @@ -186,6 +186,9 @@ $(unpack_stamp)-$(newlib_tarball): $(newlib_tarpath) $(unpack_stamp)-$(gcc_tarba mkdir -p $(stampdir) : # rm -rf $(newlib_srcdir) tar -x -f $(newlib_tarpath) + patch -p1 < debian/patches/newlib-pr119325.diff + patch -p1 < debian/patches/newlib-p2.diff + patch -p1 < debian/patches/newlib-p3.diff echo "$(newlib_tarball) unpacked." > $@ endif diff --git a/debian/rules2 b/debian/rules2 index cfed4ef..242bcb7 100644 --- a/debian/rules2 +++ b/debian/rules2 @@ -650,21 +650,11 @@ ifeq ($(DEB_TARGET_ARCH_OS),linux) endif endif -ifneq (,$(filter $(derivative),Ubuntu)) - ifneq (,$(filter $(DEB_TARGET_ARCH), ppc64el)) - ifneq (,$(filter $(distrelease),precise xenial bionic focal jammy noble oracular plucky)) - # ieee default - else - CONFARGS += --with-long-double-format=ieee - endif - endif -else ifneq (,$(filter $(derivative),Debian)) - ifneq (,$(filter $(DEB_TARGET_ARCH), ppc64el)) - ifneq (,$(filter $(distrelease),jessie stretch buster bullseye bookworm trixie)) - # ieee default - else - CONFARGS += --with-long-double-format=ieee - endif +ifneq (,$(filter $(DEB_TARGET_ARCH), ppc64el)) + ifneq (,$(filter $(distrelease), $(ppc64el_ibm128_distreleases))) + # default to IBM double + else + CONFARGS += --with-long-double-format=ieee endif endif @@ -698,6 +688,17 @@ ifneq (,$(filter $(DEB_TARGET_ARCH), amd64 i386)) endif endif +ifneq (,$(filter $(derivative),Ubuntu)) + ifeq ($(DEB_TARGET_ARCH),amd64) + # only passed in the environment by dpkg-buildpackage + ifeq ($(DEB_HOST_ARCH_VARIANT),amd64v3) + CONFARGS += --with-arch-64=x86-64-v3 + else ifeq ($(DEB_HOST_ARCH_VARIANT),amd64v4) + CONFARGS += --with-arch-64=x86-64-v4 + endif + endif +endif + ifeq ($(DEB_TARGET_ARCH),amd64) CONFARGS += --with-abi=m64 endif