118 lines
3.9 KiB
Diff
118 lines
3.9 KiB
Diff
From da3e84f3dd424c1b7fa6d86484ddcccac391e49c Mon Sep 17 00:00:00 2001
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From: Mario Limonciello <mario.limonciello@amd.com>
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Date: Thu, 5 Dec 2024 16:28:36 -0600
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Subject: cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros
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The FIELD_PREP and FIELD_GET macros improve readability and help
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to avoid shifting bugs.
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Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
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---
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drivers/cpufreq/amd-pstate.c | 45 ++++++++++++++++--------------------
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1 file changed, 20 insertions(+), 25 deletions(-)
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--- a/drivers/cpufreq/amd-pstate.c
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+++ b/drivers/cpufreq/amd-pstate.c
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@@ -22,6 +22,7 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+#include <linux/bitfield.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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@@ -88,6 +89,11 @@ static bool cppc_enabled;
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static bool amd_pstate_prefcore = true;
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static struct quirk_entry *quirks;
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+#define AMD_PSTATE_MAX_PERF_MASK GENMASK(7, 0)
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+#define AMD_PSTATE_MIN_PERF_MASK GENMASK(15, 8)
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+#define AMD_PSTATE_DES_PERF_MASK GENMASK(23, 16)
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+#define AMD_PSTATE_EPP_PERF_MASK GENMASK(31, 24)
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+
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/*
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* AMD Energy Preference Performance (EPP)
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* The EPP is used in the CCLK DPM controller to drive
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@@ -212,7 +218,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lo
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static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached)
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{
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- u64 epp;
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int ret;
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if (!cppc_req_cached) {
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@@ -222,9 +227,8 @@ static s16 msr_get_epp(struct amd_cpudat
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return ret;
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}
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}
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- epp = (cppc_req_cached >> 24) & 0xFF;
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- return (s16)epp;
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+ return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached);
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}
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DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp);
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@@ -299,12 +303,11 @@ static inline void amd_pstate_update_per
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static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp)
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{
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- int ret;
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-
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u64 value = READ_ONCE(cpudata->cppc_req_cached);
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+ int ret;
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- value &= ~GENMASK_ULL(31, 24);
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- value |= (u64)epp << 24;
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+ value &= ~AMD_PSTATE_EPP_PERF_MASK;
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+ value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp);
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
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@@ -563,18 +566,15 @@ static void amd_pstate_update(struct amd
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des_perf = 0;
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}
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- value &= ~AMD_CPPC_MIN_PERF(~0L);
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- value |= AMD_CPPC_MIN_PERF(min_perf);
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-
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- value &= ~AMD_CPPC_DES_PERF(~0L);
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- value |= AMD_CPPC_DES_PERF(des_perf);
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-
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/* limit the max perf when core performance boost feature is disabled */
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if (!cpudata->boost_supported)
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max_perf = min_t(unsigned long, nominal_perf, max_perf);
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- value &= ~AMD_CPPC_MAX_PERF(~0L);
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- value |= AMD_CPPC_MAX_PERF(max_perf);
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+ value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK |
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+ AMD_PSTATE_DES_PERF_MASK);
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+ value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf);
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+ value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf);
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+ value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf);
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if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) {
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trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq,
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@@ -1601,16 +1601,11 @@ static int amd_pstate_epp_update_limit(s
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if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
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min_perf = min(cpudata->nominal_perf, max_perf);
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- /* Initial min/max values for CPPC Performance Controls Register */
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- value &= ~AMD_CPPC_MIN_PERF(~0L);
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- value |= AMD_CPPC_MIN_PERF(min_perf);
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-
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- value &= ~AMD_CPPC_MAX_PERF(~0L);
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- value |= AMD_CPPC_MAX_PERF(max_perf);
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-
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- /* CPPC EPP feature require to set zero to the desire perf bit */
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- value &= ~AMD_CPPC_DES_PERF(~0L);
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- value |= AMD_CPPC_DES_PERF(0);
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+ value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK |
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+ AMD_PSTATE_DES_PERF_MASK);
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+ value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf);
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+ value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0);
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+ value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf);
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/* Get BIOS pre-defined epp value */
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epp = amd_pstate_get_epp(cpudata, value);
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