From da3e84f3dd424c1b7fa6d86484ddcccac391e49c Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Thu, 5 Dec 2024 16:28:36 -0600 Subject: cpufreq/amd-pstate: Use FIELD_PREP and FIELD_GET macros The FIELD_PREP and FIELD_GET macros improve readability and help to avoid shifting bugs. Signed-off-by: Mario Limonciello Reviewed-by: Gautham R. Shenoy --- drivers/cpufreq/amd-pstate.c | 45 ++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 25 deletions(-) --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -22,6 +22,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -88,6 +89,11 @@ static bool cppc_enabled; static bool amd_pstate_prefcore = true; static struct quirk_entry *quirks; +#define AMD_PSTATE_MAX_PERF_MASK GENMASK(7, 0) +#define AMD_PSTATE_MIN_PERF_MASK GENMASK(15, 8) +#define AMD_PSTATE_DES_PERF_MASK GENMASK(23, 16) +#define AMD_PSTATE_EPP_PERF_MASK GENMASK(31, 24) + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -212,7 +218,6 @@ static DEFINE_MUTEX(amd_pstate_driver_lo static s16 msr_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) { - u64 epp; int ret; if (!cppc_req_cached) { @@ -222,9 +227,8 @@ static s16 msr_get_epp(struct amd_cpudat return ret; } } - epp = (cppc_req_cached >> 24) & 0xFF; - return (s16)epp; + return FIELD_GET(AMD_PSTATE_EPP_PERF_MASK, cppc_req_cached); } DEFINE_STATIC_CALL(amd_pstate_get_epp, msr_get_epp); @@ -299,12 +303,11 @@ static inline void amd_pstate_update_per static int msr_set_epp(struct amd_cpudata *cpudata, u32 epp) { - int ret; - u64 value = READ_ONCE(cpudata->cppc_req_cached); + int ret; - value &= ~GENMASK_ULL(31, 24); - value |= (u64)epp << 24; + value &= ~AMD_PSTATE_EPP_PERF_MASK; + value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp); WRITE_ONCE(cpudata->cppc_req_cached, value); ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); @@ -563,18 +566,15 @@ static void amd_pstate_update(struct amd des_perf = 0; } - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(des_perf); - /* limit the max perf when core performance boost feature is disabled */ if (!cpudata->boost_supported) max_perf = min_t(unsigned long, nominal_perf, max_perf); - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, des_perf); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); if (trace_amd_pstate_perf_enabled() && amd_pstate_sample(cpudata)) { trace_amd_pstate_perf(min_perf, des_perf, max_perf, cpudata->freq, @@ -1601,16 +1601,11 @@ static int amd_pstate_epp_update_limit(s if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) min_perf = min(cpudata->nominal_perf, max_perf); - /* Initial min/max values for CPPC Performance Controls Register */ - value &= ~AMD_CPPC_MIN_PERF(~0L); - value |= AMD_CPPC_MIN_PERF(min_perf); - - value &= ~AMD_CPPC_MAX_PERF(~0L); - value |= AMD_CPPC_MAX_PERF(max_perf); - - /* CPPC EPP feature require to set zero to the desire perf bit */ - value &= ~AMD_CPPC_DES_PERF(~0L); - value |= AMD_CPPC_DES_PERF(0); + value &= ~(AMD_PSTATE_MAX_PERF_MASK | AMD_PSTATE_MIN_PERF_MASK | + AMD_PSTATE_DES_PERF_MASK); + value |= FIELD_PREP(AMD_PSTATE_MAX_PERF_MASK, max_perf); + value |= FIELD_PREP(AMD_PSTATE_DES_PERF_MASK, 0); + value |= FIELD_PREP(AMD_PSTATE_MIN_PERF_MASK, min_perf); /* Get BIOS pre-defined epp value */ epp = amd_pstate_get_epp(cpudata, value);