48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
From f1e8e30bef3757904d9e963f02ef297cd0c33240 Mon Sep 17 00:00:00 2001
|
|
From: Alex Deucher <alexander.deucher@amd.com>
|
|
Date: Fri, 28 Mar 2025 09:08:57 -0400
|
|
Subject: drm/amdgpu/mes12: optimize MES pipe FW version fetching
|
|
|
|
Don't fetch it again if we already have it. It seems the
|
|
registers don't reliably have the value at resume in some
|
|
cases.
|
|
|
|
Fixes: 785f0f9fe742 ("drm/amdgpu: Add mes v12_0 ip block support (v4)")
|
|
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
|
---
|
|
drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 21 ++++++++++++---------
|
|
1 file changed, 12 insertions(+), 9 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
|
|
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
|
|
@@ -1390,17 +1390,20 @@ static int mes_v12_0_queue_init(struct a
|
|
mes_v12_0_queue_init_register(ring);
|
|
}
|
|
|
|
- /* get MES scheduler/KIQ versions */
|
|
- mutex_lock(&adev->srbm_mutex);
|
|
- soc21_grbm_select(adev, 3, pipe, 0, 0);
|
|
+ if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) ||
|
|
+ ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) {
|
|
+ /* get MES scheduler/KIQ versions */
|
|
+ mutex_lock(&adev->srbm_mutex);
|
|
+ soc21_grbm_select(adev, 3, pipe, 0, 0);
|
|
|
|
- if (pipe == AMDGPU_MES_SCHED_PIPE)
|
|
- adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
|
|
- else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
|
|
- adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
|
|
+ if (pipe == AMDGPU_MES_SCHED_PIPE)
|
|
+ adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
|
|
+ else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
|
|
+ adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
|
|
|
|
- soc21_grbm_select(adev, 0, 0, 0, 0);
|
|
- mutex_unlock(&adev->srbm_mutex);
|
|
+ soc21_grbm_select(adev, 0, 0, 0, 0);
|
|
+ mutex_unlock(&adev->srbm_mutex);
|
|
+ }
|
|
|
|
return 0;
|
|
}
|