91 lines
2.9 KiB
Diff
91 lines
2.9 KiB
Diff
From e772b2eb66e5c3cf668feadab678f2a88d896189 Mon Sep 17 00:00:00 2001
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From: Rik van Riel <riel@surriel.com>
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Date: Wed, 5 Feb 2025 23:43:23 -0500
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Subject: x86/mm: get INVLPGB count max from CPUID
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The CPU advertises the maximum number of pages that can be shot down
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with one INVLPGB instruction in the CPUID data.
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Save that information for later use.
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Signed-off-by: Rik van Riel <riel@surriel.com>
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Tested-by: Manali Shukla <Manali.Shukla@amd.com>
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---
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arch/x86/Kconfig.cpu | 5 +++++
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arch/x86/include/asm/cpufeatures.h | 1 +
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arch/x86/include/asm/tlbflush.h | 7 +++++++
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arch/x86/kernel/cpu/amd.c | 8 ++++++++
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4 files changed, 21 insertions(+)
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--- a/arch/x86/Kconfig.cpu
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+++ b/arch/x86/Kconfig.cpu
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@@ -726,6 +726,10 @@ config X86_VMX_FEATURE_NAMES
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def_bool y
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depends on IA32_FEAT_CTL
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+config X86_BROADCAST_TLB_FLUSH
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+ def_bool y
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+ depends on CPU_SUP_AMD && 64BIT
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+
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menuconfig PROCESSOR_SELECT
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bool "Supported processor vendors" if EXPERT
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help
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@@ -762,6 +766,7 @@ config CPU_SUP_CYRIX_32
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config CPU_SUP_AMD
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default y
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bool "Support AMD processors" if PROCESSOR_SELECT
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+ select X86_BROADCAST_TLB_FLUSH
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help
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This enables detection, tunings and quirks for AMD processors
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--- a/arch/x86/include/asm/cpufeatures.h
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+++ b/arch/x86/include/asm/cpufeatures.h
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@@ -335,6 +335,7 @@
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#define X86_FEATURE_CLZERO (13*32+ 0) /* "clzero" CLZERO instruction */
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#define X86_FEATURE_IRPERF (13*32+ 1) /* "irperf" Instructions Retired Count */
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#define X86_FEATURE_XSAVEERPTR (13*32+ 2) /* "xsaveerptr" Always save/restore FP error pointers */
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+#define X86_FEATURE_INVLPGB (13*32+ 3) /* INVLPGB and TLBSYNC instruction supported. */
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#define X86_FEATURE_RDPRU (13*32+ 4) /* "rdpru" Read processor register at user level */
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#define X86_FEATURE_WBNOINVD (13*32+ 9) /* "wbnoinvd" WBNOINVD instruction */
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#define X86_FEATURE_AMD_IBPB (13*32+12) /* Indirect Branch Prediction Barrier */
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--- a/arch/x86/include/asm/tlbflush.h
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+++ b/arch/x86/include/asm/tlbflush.h
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@@ -183,6 +183,13 @@ static inline void cr4_init_shadow(void)
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extern unsigned long mmu_cr4_features;
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extern u32 *trampoline_cr4_features;
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+/* How many pages can we invalidate with one INVLPGB. */
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+#ifdef CONFIG_X86_BROADCAST_TLB_FLUSH
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+extern u16 invlpgb_count_max;
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+#else
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+#define invlpgb_count_max 1
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+#endif
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+
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extern void initialize_tlbstate_and_flush(void);
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/*
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -29,6 +29,8 @@
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#include "cpu.h"
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+u16 invlpgb_count_max __ro_after_init;
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+
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static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
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{
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u32 gprs[8] = { 0 };
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@@ -1135,6 +1137,12 @@ static void cpu_detect_tlb_amd(struct cp
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tlb_lli_2m[ENTRIES] = eax & mask;
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tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
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+
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+ /* Max number of pages INVLPGB can invalidate in one shot */
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+ if (boot_cpu_has(X86_FEATURE_INVLPGB)) {
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+ cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
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+ invlpgb_count_max = (edx & 0xffff) + 1;
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+ }
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}
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static const struct cpu_dev amd_cpu_dev = {
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