31 lines
985 B
Diff
31 lines
985 B
Diff
From de31d4a11e894a73ed7ef2388fb27f0bb4036de3 Mon Sep 17 00:00:00 2001
|
|
From: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
|
|
Date: Wed, 23 Oct 2024 10:21:08 +0000
|
|
Subject: cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE
|
|
|
|
MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear
|
|
it is futile, it will not take effect. Hence, return if disable (0)
|
|
argument is passed to the msr_cppc_enable()
|
|
|
|
Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
|
|
Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
|
|
---
|
|
drivers/cpufreq/amd-pstate.c | 6 ++++++
|
|
1 file changed, 6 insertions(+)
|
|
|
|
--- a/drivers/cpufreq/amd-pstate.c
|
|
+++ b/drivers/cpufreq/amd-pstate.c
|
|
@@ -341,6 +341,12 @@ static inline int msr_cppc_enable(bool e
|
|
int ret, cpu;
|
|
unsigned long logical_proc_id_mask = 0;
|
|
|
|
+ /*
|
|
+ * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared.
|
|
+ */
|
|
+ if (!enable)
|
|
+ return 0;
|
|
+
|
|
if (enable == cppc_enabled)
|
|
return 0;
|
|
|