87 lines
2.7 KiB
Diff
87 lines
2.7 KiB
Diff
From 4d73be13721834ee79ae45bd66102501f17a779d Mon Sep 17 00:00:00 2001
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From: Victor Shih <victor.shih@genesyslogic.com.tw>
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Date: Thu, 31 Jul 2025 14:57:50 +0800
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Subject: mmc: sdhci-pci-gli: Add a new function to simplify the code
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In preparation to fix replay timer timeout, add
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sdhci_gli_mask_replay_timer_timeout() function
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to simplify some of the code, allowing it to be re-used.
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Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
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Fixes: 1ae1d2d6e555 ("mmc: sdhci-pci-gli: Add Genesys Logic GL9763E support")
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Cc: stable@vger.kernel.org
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Acked-by: Adrian Hunter <adrian.hunter@intel.com>
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Link: https://lore.kernel.org/r/20250731065752.450231-2-victorshihgli@gmail.com
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Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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---
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drivers/mmc/host/sdhci-pci-gli.c | 30 ++++++++++++++++--------------
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1 file changed, 16 insertions(+), 14 deletions(-)
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--- a/drivers/mmc/host/sdhci-pci-gli.c
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+++ b/drivers/mmc/host/sdhci-pci-gli.c
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@@ -287,6 +287,20 @@
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#define GLI_MAX_TUNING_LOOP 40
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/* Genesys Logic chipset */
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+static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev)
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+{
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+ int aer;
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+ u32 value;
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+
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+ /* mask the replay timer timeout of AER */
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+ aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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+ if (aer) {
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+ pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
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+ value |= PCI_ERR_COR_REP_TIMER;
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+ pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
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+ }
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+}
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+
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static inline void gl9750_wt_on(struct sdhci_host *host)
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{
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u32 wt_value;
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@@ -607,7 +621,6 @@ static void gl9750_hw_setting(struct sdh
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{
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struct sdhci_pci_slot *slot = sdhci_priv(host);
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struct pci_dev *pdev;
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- int aer;
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u32 value;
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pdev = slot->chip->pdev;
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@@ -626,12 +639,7 @@ static void gl9750_hw_setting(struct sdh
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pci_set_power_state(pdev, PCI_D0);
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/* mask the replay timer timeout of AER */
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- aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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- if (aer) {
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- pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
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- value |= PCI_ERR_COR_REP_TIMER;
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- pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
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- }
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+ sdhci_gli_mask_replay_timer_timeout(pdev);
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gl9750_wt_off(host);
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}
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@@ -806,7 +814,6 @@ static void sdhci_gl9755_set_clock(struc
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static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
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{
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struct pci_dev *pdev = slot->chip->pdev;
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- int aer;
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u32 value;
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gl9755_wt_on(pdev);
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@@ -841,12 +848,7 @@ static void gl9755_hw_setting(struct sdh
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pci_set_power_state(pdev, PCI_D0);
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/* mask the replay timer timeout of AER */
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- aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
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- if (aer) {
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- pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value);
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- value |= PCI_ERR_COR_REP_TIMER;
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- pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value);
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- }
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+ sdhci_gli_mask_replay_timer_timeout(pdev);
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gl9755_wt_off(pdev);
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}
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