92 lines
4.2 KiB
Diff
92 lines
4.2 KiB
Diff
From e9efb8c2e0d662c1d28a95732f0a085e81c365ab Mon Sep 17 00:00:00 2001
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From: Jiwei Sun <sunjw10@lenovo.com>
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Date: Thu, 23 Jan 2025 13:51:54 +0800
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Subject: PCI: Fix link speed calculation on retrain failure
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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When pcie_failed_link_retrain() fails to retrain, it tries to revert to the
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previous link speed. However it calculates that speed from the Link
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Control 2 register without masking out non-speed bits first.
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PCIE_LNKCTL2_TLS2SPEED() converts such incorrect values to
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PCI_SPEED_UNKNOWN (0xff), which in turn causes a WARN splat in
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pcie_set_target_speed():
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pci 0000:00:01.1: [1022:14ed] type 01 class 0x060400 PCIe Root Port
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pci 0000:00:01.1: broken device, retraining non-functional downstream link at 2.5GT/s
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pci 0000:00:01.1: retraining failed
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WARNING: CPU: 1 PID: 1 at drivers/pci/pcie/bwctrl.c:168 pcie_set_target_speed
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RDX: 0000000000000001 RSI: 00000000000000ff RDI: ffff9acd82efa000
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pcie_failed_link_retrain
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pci_device_add
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pci_scan_single_device
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Mask out the non-speed bits in PCIE_LNKCTL2_TLS2SPEED() and
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PCIE_LNKCAP_SLS2SPEED() so they don't incorrectly return PCI_SPEED_UNKNOWN.
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Fixes: de9a6c8d5dbf ("PCI/bwctrl: Add pcie_set_target_speed() to set PCIe Link Speed")
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Reported-by: Andrew <andreasx0@protonmail.com>
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Closes: https://lore.kernel.org/r/7iNzXbCGpf8yUMJZBQjLdbjPcXrEJqBxy5-bHfppz0ek-h4_-G93b1KUrm106r2VNF2FV_sSq0nENv4RsRIUGnlYZMlQr2ZD2NyB5sdj5aU=@protonmail.com/
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Suggested-by: Maciej W. Rozycki <macro@orcam.me.uk>
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Suggested-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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Signed-off-by: Jiwei Sun <sunjw10@lenovo.com>
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[bhelgaas: commit log, add details from https://lore.kernel.org/r/1c92ef6bcb314ee6977839b46b393282e4f52e74.1750684771.git.lukas@wunner.de]
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Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
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Cc: stable@vger.kernel.org # v6.13+
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Link: https://patch.msgid.link/20250123055155.22648-2-sjiwei@163.com
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---
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drivers/pci/pci.h | 32 +++++++++++++++++++-------------
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1 file changed, 19 insertions(+), 13 deletions(-)
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--- a/drivers/pci/pci.h
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+++ b/drivers/pci/pci.h
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@@ -391,12 +391,14 @@ void pci_bus_put(struct pci_bus *bus);
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#define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
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({ \
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- ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
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- (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
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- (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
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- (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
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- (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
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- (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
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+ u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \
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+ \
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+ (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
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+ lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
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+ lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
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+ lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
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+ lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
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+ lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
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PCI_SPEED_UNKNOWN); \
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})
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@@ -411,13 +413,17 @@ void pci_bus_put(struct pci_bus *bus);
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PCI_SPEED_UNKNOWN)
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#define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
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- ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
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- (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
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- (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
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- (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
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- (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
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- (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
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- PCI_SPEED_UNKNOWN)
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+({ \
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+ u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \
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+ \
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+ (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
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+ lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
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+ lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
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+ lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
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+ lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
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+ lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
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+ PCI_SPEED_UNKNOWN); \
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+})
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/* PCIe speed to Mb/s reduced by encoding overhead */
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#define PCIE_SPEED2MBS_ENC(speed) \
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