Konstantin Demin
8cbaf1dea2
3rd patchs (in alphabetical order): - bbr3 - ntsync5 - openwrt - pf-kernel - xanmod - zen no configuration changes for now
359 lines
11 KiB
Diff
359 lines
11 KiB
Diff
From b5c83c40540298a39f8314034b705f1236b17a9f Mon Sep 17 00:00:00 2001
|
|
From: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
|
|
Date: Fri, 13 Sep 2024 15:47:58 +0000
|
|
Subject: perf/x86/rapl: Modify the generic variable names to *_pkg*
|
|
|
|
Prep for addition of power_per_core PMU to handle core scope energy
|
|
consumption for AMD CPUs.
|
|
|
|
Replace the generic names with *_pkg*, to differentiate between the
|
|
scopes of the two different PMUs and their variables.
|
|
|
|
No functional change.
|
|
|
|
Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
|
|
---
|
|
arch/x86/events/rapl.c | 118 ++++++++++++++++++++---------------------
|
|
1 file changed, 59 insertions(+), 59 deletions(-)
|
|
|
|
--- a/arch/x86/events/rapl.c
|
|
+++ b/arch/x86/events/rapl.c
|
|
@@ -70,18 +70,18 @@ MODULE_LICENSE("GPL");
|
|
/*
|
|
* RAPL energy status counters
|
|
*/
|
|
-enum perf_rapl_events {
|
|
+enum perf_rapl_pkg_events {
|
|
PERF_RAPL_PP0 = 0, /* all cores */
|
|
PERF_RAPL_PKG, /* entire package */
|
|
PERF_RAPL_RAM, /* DRAM */
|
|
PERF_RAPL_PP1, /* gpu */
|
|
PERF_RAPL_PSYS, /* psys */
|
|
|
|
- PERF_RAPL_MAX,
|
|
- NR_RAPL_DOMAINS = PERF_RAPL_MAX,
|
|
+ PERF_RAPL_PKG_EVENTS_MAX,
|
|
+ NR_RAPL_PKG_DOMAINS = PERF_RAPL_PKG_EVENTS_MAX,
|
|
};
|
|
|
|
-static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = {
|
|
+static const char *const rapl_pkg_domain_names[NR_RAPL_PKG_DOMAINS] __initconst = {
|
|
"pp0-core",
|
|
"package",
|
|
"dram",
|
|
@@ -126,16 +126,16 @@ enum rapl_unit_quirk {
|
|
};
|
|
|
|
struct rapl_model {
|
|
- struct perf_msr *rapl_msrs;
|
|
- unsigned long events;
|
|
+ struct perf_msr *rapl_pkg_msrs;
|
|
+ unsigned long pkg_events;
|
|
unsigned int msr_power_unit;
|
|
enum rapl_unit_quirk unit_quirk;
|
|
};
|
|
|
|
/* 1/2^hw_unit Joule */
|
|
-static int rapl_hw_unit[NR_RAPL_DOMAINS] __read_mostly;
|
|
-static struct rapl_pmus *rapl_pmus;
|
|
-static unsigned int rapl_cntr_mask;
|
|
+static int rapl_pkg_hw_unit[NR_RAPL_PKG_DOMAINS] __read_mostly;
|
|
+static struct rapl_pmus *rapl_pmus_pkg;
|
|
+static unsigned int rapl_pkg_cntr_mask;
|
|
static u64 rapl_timer_ms;
|
|
static struct perf_msr *rapl_msrs;
|
|
static struct rapl_model *rapl_model;
|
|
@@ -149,7 +149,7 @@ static struct rapl_model *rapl_model;
|
|
* considered as either pkg-scope or die-scope, and we are considering
|
|
* them as die-scope.
|
|
*/
|
|
-#define rapl_pmu_is_pkg_scope() \
|
|
+#define rapl_pkg_pmu_is_pkg_scope() \
|
|
(boot_cpu_data.x86_vendor == X86_VENDOR_AMD || \
|
|
boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
|
|
|
|
@@ -159,7 +159,7 @@ static struct rapl_model *rapl_model;
|
|
*/
|
|
static inline unsigned int get_rapl_pmu_idx(int cpu)
|
|
{
|
|
- return rapl_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) :
|
|
+ return rapl_pkg_pmu_is_pkg_scope() ? topology_logical_package_id(cpu) :
|
|
topology_logical_die_id(cpu);
|
|
}
|
|
|
|
@@ -172,7 +172,7 @@ static inline u64 rapl_read_counter(stru
|
|
|
|
static inline u64 rapl_scale(u64 v, int cfg)
|
|
{
|
|
- if (cfg > NR_RAPL_DOMAINS) {
|
|
+ if (cfg > NR_RAPL_PKG_DOMAINS) {
|
|
pr_warn("Invalid domain %d, failed to scale data\n", cfg);
|
|
return v;
|
|
}
|
|
@@ -182,7 +182,7 @@ static inline u64 rapl_scale(u64 v, int
|
|
* or use ldexp(count, -32).
|
|
* Watts = Joules/Time delta
|
|
*/
|
|
- return v << (32 - rapl_hw_unit[cfg - 1]);
|
|
+ return v << (32 - rapl_pkg_hw_unit[cfg - 1]);
|
|
}
|
|
|
|
static u64 rapl_event_update(struct perf_event *event)
|
|
@@ -342,7 +342,7 @@ static int rapl_pmu_event_init(struct pe
|
|
struct rapl_pmu *rapl_pmu;
|
|
|
|
/* only look at RAPL events */
|
|
- if (event->attr.type != rapl_pmus->pmu.type)
|
|
+ if (event->attr.type != rapl_pmus_pkg->pmu.type)
|
|
return -ENOENT;
|
|
|
|
/* check only supported bits are set */
|
|
@@ -352,14 +352,14 @@ static int rapl_pmu_event_init(struct pe
|
|
if (event->cpu < 0)
|
|
return -EINVAL;
|
|
|
|
- if (!cfg || cfg >= NR_RAPL_DOMAINS + 1)
|
|
+ if (!cfg || cfg >= NR_RAPL_PKG_DOMAINS + 1)
|
|
return -EINVAL;
|
|
|
|
- cfg = array_index_nospec((long)cfg, NR_RAPL_DOMAINS + 1);
|
|
+ cfg = array_index_nospec((long)cfg, NR_RAPL_PKG_DOMAINS + 1);
|
|
bit = cfg - 1;
|
|
|
|
/* check event supported */
|
|
- if (!(rapl_cntr_mask & (1 << bit)))
|
|
+ if (!(rapl_pkg_cntr_mask & (1 << bit)))
|
|
return -EINVAL;
|
|
|
|
/* unsupported modes and filters */
|
|
@@ -367,11 +367,11 @@ static int rapl_pmu_event_init(struct pe
|
|
return -EINVAL;
|
|
|
|
rapl_pmu_idx = get_rapl_pmu_idx(event->cpu);
|
|
- if (rapl_pmu_idx >= rapl_pmus->nr_rapl_pmu)
|
|
+ if (rapl_pmu_idx >= rapl_pmus_pkg->nr_rapl_pmu)
|
|
return -EINVAL;
|
|
|
|
/* must be done before validate_group */
|
|
- rapl_pmu = rapl_pmus->rapl_pmu[rapl_pmu_idx];
|
|
+ rapl_pmu = rapl_pmus_pkg->rapl_pmu[rapl_pmu_idx];
|
|
if (!rapl_pmu)
|
|
return -EINVAL;
|
|
|
|
@@ -525,11 +525,11 @@ static struct perf_msr intel_rapl_spr_ms
|
|
};
|
|
|
|
/*
|
|
- * Force to PERF_RAPL_MAX size due to:
|
|
- * - perf_msr_probe(PERF_RAPL_MAX)
|
|
+ * Force to PERF_RAPL_PKG_EVENTS_MAX size due to:
|
|
+ * - perf_msr_probe(PERF_RAPL_PKG_EVENTS_MAX)
|
|
* - want to use same event codes across both architectures
|
|
*/
|
|
-static struct perf_msr amd_rapl_msrs[] = {
|
|
+static struct perf_msr amd_rapl_pkg_msrs[] = {
|
|
[PERF_RAPL_PP0] = { 0, &rapl_events_cores_group, NULL, false, 0 },
|
|
[PERF_RAPL_PKG] = { MSR_AMD_PKG_ENERGY_STATUS, &rapl_events_pkg_group, test_msr, false, RAPL_MSR_MASK },
|
|
[PERF_RAPL_RAM] = { 0, &rapl_events_ram_group, NULL, false, 0 },
|
|
@@ -545,8 +545,8 @@ static int rapl_check_hw_unit(void)
|
|
/* protect rdmsrl() to handle virtualization */
|
|
if (rdmsrl_safe(rapl_model->msr_power_unit, &msr_rapl_power_unit_bits))
|
|
return -1;
|
|
- for (i = 0; i < NR_RAPL_DOMAINS; i++)
|
|
- rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
|
|
+ for (i = 0; i < NR_RAPL_PKG_DOMAINS; i++)
|
|
+ rapl_pkg_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL;
|
|
|
|
switch (rapl_model->unit_quirk) {
|
|
/*
|
|
@@ -556,11 +556,11 @@ static int rapl_check_hw_unit(void)
|
|
* of 2. Datasheet, September 2014, Reference Number: 330784-001 "
|
|
*/
|
|
case RAPL_UNIT_QUIRK_INTEL_HSW:
|
|
- rapl_hw_unit[PERF_RAPL_RAM] = 16;
|
|
+ rapl_pkg_hw_unit[PERF_RAPL_RAM] = 16;
|
|
break;
|
|
/* SPR uses a fixed energy unit for Psys domain. */
|
|
case RAPL_UNIT_QUIRK_INTEL_SPR:
|
|
- rapl_hw_unit[PERF_RAPL_PSYS] = 0;
|
|
+ rapl_pkg_hw_unit[PERF_RAPL_PSYS] = 0;
|
|
break;
|
|
default:
|
|
break;
|
|
@@ -575,9 +575,9 @@ static int rapl_check_hw_unit(void)
|
|
* if hw unit is 32, then we use 2 ms 1/200/2
|
|
*/
|
|
rapl_timer_ms = 2;
|
|
- if (rapl_hw_unit[0] < 32) {
|
|
+ if (rapl_pkg_hw_unit[0] < 32) {
|
|
rapl_timer_ms = (1000 / (2 * 100));
|
|
- rapl_timer_ms *= (1ULL << (32 - rapl_hw_unit[0] - 1));
|
|
+ rapl_timer_ms *= (1ULL << (32 - rapl_pkg_hw_unit[0] - 1));
|
|
}
|
|
return 0;
|
|
}
|
|
@@ -587,12 +587,12 @@ static void __init rapl_advertise(void)
|
|
int i;
|
|
|
|
pr_info("API unit is 2^-32 Joules, %d fixed counters, %llu ms ovfl timer\n",
|
|
- hweight32(rapl_cntr_mask), rapl_timer_ms);
|
|
+ hweight32(rapl_pkg_cntr_mask), rapl_timer_ms);
|
|
|
|
- for (i = 0; i < NR_RAPL_DOMAINS; i++) {
|
|
- if (rapl_cntr_mask & (1 << i)) {
|
|
+ for (i = 0; i < NR_RAPL_PKG_DOMAINS; i++) {
|
|
+ if (rapl_pkg_cntr_mask & (1 << i)) {
|
|
pr_info("hw unit of domain %s 2^-%d Joules\n",
|
|
- rapl_domain_names[i], rapl_hw_unit[i]);
|
|
+ rapl_pkg_domain_names[i], rapl_pkg_hw_unit[i]);
|
|
}
|
|
}
|
|
}
|
|
@@ -681,71 +681,71 @@ static int __init init_rapl_pmus(struct
|
|
}
|
|
|
|
static struct rapl_model model_snb = {
|
|
- .events = BIT(PERF_RAPL_PP0) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PP0) |
|
|
BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_PP1),
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_snbep = {
|
|
- .events = BIT(PERF_RAPL_PP0) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PP0) |
|
|
BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_RAM),
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_hsw = {
|
|
- .events = BIT(PERF_RAPL_PP0) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PP0) |
|
|
BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_RAM) |
|
|
BIT(PERF_RAPL_PP1),
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_hsx = {
|
|
- .events = BIT(PERF_RAPL_PP0) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PP0) |
|
|
BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_RAM),
|
|
.unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_knl = {
|
|
- .events = BIT(PERF_RAPL_PKG) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_RAM),
|
|
.unit_quirk = RAPL_UNIT_QUIRK_INTEL_HSW,
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_skl = {
|
|
- .events = BIT(PERF_RAPL_PP0) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PP0) |
|
|
BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_RAM) |
|
|
BIT(PERF_RAPL_PP1) |
|
|
BIT(PERF_RAPL_PSYS),
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_spr = {
|
|
- .events = BIT(PERF_RAPL_PP0) |
|
|
+ .pkg_events = BIT(PERF_RAPL_PP0) |
|
|
BIT(PERF_RAPL_PKG) |
|
|
BIT(PERF_RAPL_RAM) |
|
|
BIT(PERF_RAPL_PSYS),
|
|
.unit_quirk = RAPL_UNIT_QUIRK_INTEL_SPR,
|
|
.msr_power_unit = MSR_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = intel_rapl_spr_msrs,
|
|
+ .rapl_pkg_msrs = intel_rapl_spr_msrs,
|
|
};
|
|
|
|
static struct rapl_model model_amd_hygon = {
|
|
- .events = BIT(PERF_RAPL_PKG),
|
|
+ .pkg_events = BIT(PERF_RAPL_PKG),
|
|
.msr_power_unit = MSR_AMD_RAPL_POWER_UNIT,
|
|
- .rapl_msrs = amd_rapl_msrs,
|
|
+ .rapl_pkg_msrs = amd_rapl_pkg_msrs,
|
|
};
|
|
|
|
static const struct x86_cpu_id rapl_model_match[] __initconst = {
|
|
@@ -801,11 +801,11 @@ MODULE_DEVICE_TABLE(x86cpu, rapl_model_m
|
|
static int __init rapl_pmu_init(void)
|
|
{
|
|
const struct x86_cpu_id *id;
|
|
- int rapl_pmu_scope = PERF_PMU_SCOPE_DIE;
|
|
+ int rapl_pkg_pmu_scope = PERF_PMU_SCOPE_DIE;
|
|
int ret;
|
|
|
|
- if (rapl_pmu_is_pkg_scope())
|
|
- rapl_pmu_scope = PERF_PMU_SCOPE_PKG;
|
|
+ if (rapl_pkg_pmu_is_pkg_scope())
|
|
+ rapl_pkg_pmu_scope = PERF_PMU_SCOPE_PKG;
|
|
|
|
id = x86_match_cpu(rapl_model_match);
|
|
if (!id)
|
|
@@ -813,20 +813,20 @@ static int __init rapl_pmu_init(void)
|
|
|
|
rapl_model = (struct rapl_model *) id->driver_data;
|
|
|
|
- rapl_msrs = rapl_model->rapl_msrs;
|
|
+ rapl_msrs = rapl_model->rapl_pkg_msrs;
|
|
|
|
- rapl_cntr_mask = perf_msr_probe(rapl_msrs, PERF_RAPL_MAX,
|
|
- false, (void *) &rapl_model->events);
|
|
+ rapl_pkg_cntr_mask = perf_msr_probe(rapl_msrs, PERF_RAPL_PKG_EVENTS_MAX,
|
|
+ false, (void *) &rapl_model->pkg_events);
|
|
|
|
ret = rapl_check_hw_unit();
|
|
if (ret)
|
|
return ret;
|
|
|
|
- ret = init_rapl_pmus(&rapl_pmus, rapl_pmu_scope);
|
|
+ ret = init_rapl_pmus(&rapl_pmus_pkg, rapl_pkg_pmu_scope);
|
|
if (ret)
|
|
return ret;
|
|
|
|
- ret = perf_pmu_register(&rapl_pmus->pmu, "power", -1);
|
|
+ ret = perf_pmu_register(&rapl_pmus_pkg->pmu, "power", -1);
|
|
if (ret)
|
|
goto out;
|
|
|
|
@@ -835,14 +835,14 @@ static int __init rapl_pmu_init(void)
|
|
|
|
out:
|
|
pr_warn("Initialization failed (%d), disabled\n", ret);
|
|
- cleanup_rapl_pmus(rapl_pmus);
|
|
+ cleanup_rapl_pmus(rapl_pmus_pkg);
|
|
return ret;
|
|
}
|
|
module_init(rapl_pmu_init);
|
|
|
|
static void __exit intel_rapl_exit(void)
|
|
{
|
|
- perf_pmu_unregister(&rapl_pmus->pmu);
|
|
- cleanup_rapl_pmus(rapl_pmus);
|
|
+ perf_pmu_unregister(&rapl_pmus_pkg->pmu);
|
|
+ cleanup_rapl_pmus(rapl_pmus_pkg);
|
|
}
|
|
module_exit(intel_rapl_exit);
|