48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
From feadcb68955511723dbc2cad800e0524625d62c5 Mon Sep 17 00:00:00 2001
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From: Alex Deucher <alexander.deucher@amd.com>
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Date: Fri, 28 Mar 2025 09:08:57 -0400
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Subject: drm/amdgpu/mes12: optimize MES pipe FW version fetching
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Don't fetch it again if we already have it. It seems the
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registers don't reliably have the value at resume in some
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cases.
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Fixes: 785f0f9fe742 ("drm/amdgpu: Add mes v12_0 ip block support (v4)")
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Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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---
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drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 21 ++++++++++++---------
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1 file changed, 12 insertions(+), 9 deletions(-)
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--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
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+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c
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@@ -1390,17 +1390,20 @@ static int mes_v12_0_queue_init(struct a
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mes_v12_0_queue_init_register(ring);
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}
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- /* get MES scheduler/KIQ versions */
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- mutex_lock(&adev->srbm_mutex);
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- soc21_grbm_select(adev, 3, pipe, 0, 0);
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+ if (((pipe == AMDGPU_MES_SCHED_PIPE) && !adev->mes.sched_version) ||
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+ ((pipe == AMDGPU_MES_KIQ_PIPE) && !adev->mes.kiq_version)) {
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+ /* get MES scheduler/KIQ versions */
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+ mutex_lock(&adev->srbm_mutex);
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+ soc21_grbm_select(adev, 3, pipe, 0, 0);
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- if (pipe == AMDGPU_MES_SCHED_PIPE)
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- adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
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- else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
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- adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
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+ if (pipe == AMDGPU_MES_SCHED_PIPE)
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+ adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
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+ else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
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+ adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO);
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- soc21_grbm_select(adev, 0, 0, 0, 0);
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- mutex_unlock(&adev->srbm_mutex);
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+ soc21_grbm_select(adev, 0, 0, 0, 0);
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+ mutex_unlock(&adev->srbm_mutex);
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+ }
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return 0;
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}
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