Konstantin Demin
8cbaf1dea2
3rd patchs (in alphabetical order): - bbr3 - ntsync5 - openwrt - pf-kernel - xanmod - zen no configuration changes for now
170 lines
5.9 KiB
Diff
170 lines
5.9 KiB
Diff
From 68d89574b86625f4bd7a784fe9bcc221dc290e4f Mon Sep 17 00:00:00 2001
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From: Mario Limonciello <mario.limonciello@amd.com>
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Date: Thu, 5 Sep 2024 11:30:04 -0500
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Subject: cpufreq: amd-pstate: Merge amd_pstate_highest_perf_set() into
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amd_get_boost_ratio_numerator()
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The special case in amd_pstate_highest_perf_set() is the value used
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for calculating the boost numerator. Merge this into
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amd_get_boost_ratio_numerator() and then use that to calculate boost
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ratio.
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This allows dropping more special casing of the highest perf value.
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Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
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Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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Reviewed-by: Gautham R. Shenoy <gautham.sheoy@amd.com>
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---
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Documentation/admin-guide/pm/amd-pstate.rst | 3 +-
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arch/x86/kernel/acpi/cppc.c | 16 +++++++
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drivers/cpufreq/amd-pstate.c | 52 ++++-----------------
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3 files changed, 28 insertions(+), 43 deletions(-)
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--- a/Documentation/admin-guide/pm/amd-pstate.rst
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+++ b/Documentation/admin-guide/pm/amd-pstate.rst
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@@ -251,7 +251,8 @@ performance supported in `AMD CPPC Perfo
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In some ASICs, the highest CPPC performance is not the one in the ``_CPC``
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table, so we need to expose it to sysfs. If boost is not active, but
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still supported, this maximum frequency will be larger than the one in
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-``cpuinfo``.
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+``cpuinfo``. On systems that support preferred core, the driver will have
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+different values for some cores than others.
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This attribute is read-only.
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``amd_pstate_lowest_nonlinear_freq``
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--- a/arch/x86/kernel/acpi/cppc.c
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+++ b/arch/x86/kernel/acpi/cppc.c
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@@ -9,6 +9,7 @@
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#include <asm/processor.h>
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#include <asm/topology.h>
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+#define CPPC_HIGHEST_PERF_PERFORMANCE 196
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#define CPPC_HIGHEST_PERF_PREFCORE 166
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enum amd_pref_core {
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@@ -245,6 +246,21 @@ int amd_get_boost_ratio_numerator(unsign
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*numerator = boost_numerator;
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return 0;
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}
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+
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+ /*
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+ * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f,
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+ * the highest performance level is set to 196.
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+ * https://bugzilla.kernel.org/show_bug.cgi?id=218759
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+ */
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+ if (cpu_feature_enabled(X86_FEATURE_ZEN4)) {
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+ switch (boot_cpu_data.x86_model) {
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+ case 0x70 ... 0x7f:
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+ *numerator = CPPC_HIGHEST_PERF_PERFORMANCE;
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+ return 0;
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+ default:
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+ break;
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+ }
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+ }
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*numerator = CPPC_HIGHEST_PERF_PREFCORE;
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return 0;
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--- a/drivers/cpufreq/amd-pstate.c
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+++ b/drivers/cpufreq/amd-pstate.c
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@@ -52,8 +52,6 @@
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#define AMD_PSTATE_TRANSITION_LATENCY 20000
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#define AMD_PSTATE_TRANSITION_DELAY 1000
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#define AMD_PSTATE_FAST_CPPC_TRANSITION_DELAY 600
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-#define CPPC_HIGHEST_PERF_PERFORMANCE 196
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-#define CPPC_HIGHEST_PERF_DEFAULT 166
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#define AMD_CPPC_EPP_PERFORMANCE 0x00
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#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80
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@@ -398,43 +396,17 @@ static inline int amd_pstate_enable(bool
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return static_call(amd_pstate_enable)(enable);
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}
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-static u32 amd_pstate_highest_perf_set(struct amd_cpudata *cpudata)
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-{
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- struct cpuinfo_x86 *c = &cpu_data(0);
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-
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- /*
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- * For AMD CPUs with Family ID 19H and Model ID range 0x70 to 0x7f,
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- * the highest performance level is set to 196.
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- * https://bugzilla.kernel.org/show_bug.cgi?id=218759
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- */
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- if (c->x86 == 0x19 && (c->x86_model >= 0x70 && c->x86_model <= 0x7f))
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- return CPPC_HIGHEST_PERF_PERFORMANCE;
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-
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- return CPPC_HIGHEST_PERF_DEFAULT;
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-}
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-
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static int pstate_init_perf(struct amd_cpudata *cpudata)
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{
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u64 cap1;
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- u32 highest_perf;
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int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1,
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&cap1);
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if (ret)
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return ret;
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- /* For platforms that do not support the preferred core feature, the
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- * highest_pef may be configured with 166 or 255, to avoid max frequency
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- * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as
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- * the default max perf.
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- */
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- if (cpudata->hw_prefcore)
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- highest_perf = amd_pstate_highest_perf_set(cpudata);
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- else
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- highest_perf = AMD_CPPC_HIGHEST_PERF(cap1);
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-
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- WRITE_ONCE(cpudata->highest_perf, highest_perf);
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- WRITE_ONCE(cpudata->max_limit_perf, highest_perf);
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+ WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1));
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+ WRITE_ONCE(cpudata->max_limit_perf, AMD_CPPC_HIGHEST_PERF(cap1));
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WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1));
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WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1));
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WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1));
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@@ -446,19 +418,13 @@ static int pstate_init_perf(struct amd_c
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static int cppc_init_perf(struct amd_cpudata *cpudata)
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{
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struct cppc_perf_caps cppc_perf;
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- u32 highest_perf;
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int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
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if (ret)
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return ret;
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- if (cpudata->hw_prefcore)
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- highest_perf = amd_pstate_highest_perf_set(cpudata);
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- else
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- highest_perf = cppc_perf.highest_perf;
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-
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- WRITE_ONCE(cpudata->highest_perf, highest_perf);
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- WRITE_ONCE(cpudata->max_limit_perf, highest_perf);
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+ WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf);
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+ WRITE_ONCE(cpudata->max_limit_perf, cppc_perf.highest_perf);
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WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
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WRITE_ONCE(cpudata->lowest_nonlinear_perf,
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cppc_perf.lowest_nonlinear_perf);
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@@ -944,8 +910,8 @@ static u32 amd_pstate_get_transition_lat
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static int amd_pstate_init_freq(struct amd_cpudata *cpudata)
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{
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int ret;
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- u32 min_freq;
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- u32 highest_perf, max_freq;
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+ u32 min_freq, max_freq;
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+ u64 numerator;
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u32 nominal_perf, nominal_freq;
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u32 lowest_nonlinear_perf, lowest_nonlinear_freq;
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u32 boost_ratio, lowest_nonlinear_ratio;
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@@ -967,8 +933,10 @@ static int amd_pstate_init_freq(struct a
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nominal_perf = READ_ONCE(cpudata->nominal_perf);
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- highest_perf = READ_ONCE(cpudata->highest_perf);
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- boost_ratio = div_u64(highest_perf << SCHED_CAPACITY_SHIFT, nominal_perf);
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+ ret = amd_get_boost_ratio_numerator(cpudata->cpu, &numerator);
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+ if (ret)
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+ return ret;
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+ boost_ratio = div_u64(numerator << SCHED_CAPACITY_SHIFT, nominal_perf);
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max_freq = (nominal_freq * boost_ratio >> SCHED_CAPACITY_SHIFT) * 1000;
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lowest_nonlinear_perf = READ_ONCE(cpudata->lowest_nonlinear_perf);
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