From edf899b17950e1b926889b501e06c86dd867bac0 Mon Sep 17 00:00:00 2001 From: Basavaraj Natikar Date: Tue, 12 Nov 2024 22:33:07 +0530 Subject: [PATCH 2/2] platform/x86/amd: amd_3d_vcache: Add sysfs ABI documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add documentation for the amd_3d_vcache sysfs bus platform driver interface so that userspace applications can use it to change mode preferences, either frequency or cache. Co-developed-by: Perry Yuan Signed-off-by: Perry Yuan Co-developed-by: Mario Limonciello Signed-off-by: Mario Limonciello Reviewed-by: Shyam Sundar S K Reviewed-by: Armin Wolf Reviewed-by: Ilpo Järvinen Signed-off-by: Basavaraj Natikar Link: https://lore.kernel.org/r/20241112170307.3745777-3-Basavaraj.Natikar@amd.com Signed-off-by: Ilpo Järvinen Signed-off-by: Alexandre Frade --- .../sysfs-bus-platform-drivers-amd_x3d_vcache | 12 ++++++++++++ MAINTAINERS | 1 + 2 files changed, 13 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache @@ -0,0 +1,12 @@ +What: /sys/bus/platform/drivers/amd_x3d_vcache/AMDI0101:00/amd_x3d_mode +Date: November 2024 +KernelVersion: 6.13 +Contact: Basavaraj Natikar +Description: (RW) AMD 3D V-Cache optimizer allows users to switch CPU core + rankings dynamically. + + This file switches between these two modes: + - "frequency" cores within the faster CCD are prioritized before + those in the slower CCD. + - "cache" cores within the larger L3 CCD are prioritized before + those in the smaller L3 CCD. --- a/MAINTAINERS +++ b/MAINTAINERS @@ -970,6 +970,7 @@ M: Basavaraj Natikar L: platform-driver-x86@vger.kernel.org S: Supported +F: Documentation/ABI/testing/sysfs-bus-platform-drivers-amd_x3d_vcache F: drivers/platform/x86/amd/x3d_vcache.c AMD ADDRESS TRANSLATION LIBRARY (ATL)