1
0

release 6.11.6

This commit is contained in:
2024-11-01 15:46:17 +03:00
parent 352b17054d
commit a84cf6e84b
24 changed files with 178 additions and 577 deletions

View File

@@ -48,7 +48,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
struct quirk_entry {
u32 nominal_freq;
u32 lowest_freq;
@@ -1392,7 +1388,7 @@ static ssize_t amd_pstate_show_status(ch
@@ -1402,7 +1398,7 @@ static ssize_t amd_pstate_show_status(ch
return sysfs_emit(buf, "%s\n", amd_pstate_mode_string[cppc_state]);
}
@@ -57,7 +57,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
{
int mode_idx;
@@ -1409,6 +1405,7 @@ static int amd_pstate_update_status(cons
@@ -1419,6 +1415,7 @@ static int amd_pstate_update_status(cons
return 0;
}

View File

@@ -14,7 +14,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1595,7 +1595,7 @@ static void amd_pstate_epp_cpu_exit(stru
@@ -1605,7 +1605,7 @@ static void amd_pstate_epp_cpu_exit(stru
pr_debug("CPU %d exiting\n", policy->cpu);
}
@@ -23,7 +23,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
{
struct amd_cpudata *cpudata = policy->driver_data;
u32 max_perf, min_perf, min_limit_perf, max_limit_perf;
@@ -1645,7 +1645,7 @@ static void amd_pstate_epp_update_limit(
@@ -1655,7 +1655,7 @@ static void amd_pstate_epp_update_limit(
* This return value can only be negative for shared_memory
* systems where EPP register read/write not supported.
*/
@@ -32,7 +32,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
}
if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
@@ -1658,12 +1658,13 @@ static void amd_pstate_epp_update_limit(
@@ -1668,12 +1668,13 @@ static void amd_pstate_epp_update_limit(
}
WRITE_ONCE(cpudata->cppc_req_cached, value);
@@ -47,7 +47,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
if (!policy->cpuinfo.max_freq)
return -ENODEV;
@@ -1673,7 +1674,9 @@ static int amd_pstate_epp_set_policy(str
@@ -1683,7 +1684,9 @@ static int amd_pstate_epp_set_policy(str
cpudata->policy = policy->policy;

View File

@@ -200,7 +200,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
ret = amd_pstate_init_freq(cpudata);
if (ret)
goto free_cpudata1;
@@ -1493,12 +1479,12 @@ static int amd_pstate_epp_cpu_init(struc
@@ -1503,12 +1489,12 @@ static int amd_pstate_epp_cpu_init(struc
cpudata->cpu = policy->cpu;
cpudata->epp_policy = 0;
@@ -215,7 +215,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
ret = amd_pstate_init_freq(cpudata);
if (ret)
goto free_cpudata1;
@@ -1960,6 +1946,12 @@ static int __init amd_pstate_init(void)
@@ -1970,6 +1956,12 @@ static int __init amd_pstate_init(void)
static_call_update(amd_pstate_update_perf, cppc_update_perf);
}

View File

@@ -13,7 +13,7 @@ Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1786,7 +1786,7 @@ static int __init amd_pstate_set_driver(
@@ -1796,7 +1796,7 @@ static int __init amd_pstate_set_driver(
return -EINVAL;
}

View File

@@ -93,7 +93,7 @@ Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
u32 min_perf, u32 des_perf,
u32 max_perf, bool fast_switch)
{
@@ -1909,9 +1909,9 @@ static int __init amd_pstate_init(void)
@@ -1919,9 +1919,9 @@ static int __init amd_pstate_init(void)
current_pstate_driver->adjust_perf = amd_pstate_adjust_perf;
} else {
pr_debug("AMD CPPC shared memory based functionality is supported\n");

View File

@@ -47,7 +47,7 @@ Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
ret = freq_qos_add_request(&policy->constraints, &cpudata->req[1],
FREQ_QOS_MAX, policy->cpuinfo.max_freq);
if (ret < 0) {
@@ -1736,6 +1729,13 @@ static int amd_pstate_epp_resume(struct
@@ -1746,6 +1739,13 @@ static int amd_pstate_epp_resume(struct
return 0;
}
@@ -61,7 +61,7 @@ Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
static struct cpufreq_driver amd_pstate_driver = {
.flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
.verify = amd_pstate_verify,
@@ -1749,6 +1749,7 @@ static struct cpufreq_driver amd_pstate_
@@ -1759,6 +1759,7 @@ static struct cpufreq_driver amd_pstate_
.update_limits = amd_pstate_update_limits,
.name = "amd-pstate",
.attr = amd_pstate_attr,
@@ -69,7 +69,7 @@ Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
};
static struct cpufreq_driver amd_pstate_epp_driver = {
@@ -1765,6 +1766,7 @@ static struct cpufreq_driver amd_pstate_
@@ -1775,6 +1776,7 @@ static struct cpufreq_driver amd_pstate_
.set_boost = amd_pstate_set_boost,
.name = "amd-pstate-epp",
.attr = amd_pstate_epp_attr,

View File

@@ -1,42 +0,0 @@
From d1216c052bedbf6d79e4b0261e2f09e17c66ffd3 Mon Sep 17 00:00:00 2001
From: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
Date: Fri, 4 Oct 2024 12:23:04 +0000
Subject: cpufreq/amd-pstate: Fix amd_pstate mode switch on shared memory
systems
While switching the driver mode between active and passive, Collaborative
Processor Performance Control (CPPC) is disabled in
amd_pstate_unregister_driver(). But, it is not enabled back while registering
the new driver (passive or active). This leads to the new driver mode not
working correctly, so enable it back in amd_pstate_register_driver().
Fixes: 3ca7bc818d8c ("cpufreq: amd-pstate: Add guided mode control support via sysfs")
Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
---
drivers/cpufreq/amd-pstate.c | 10 ++++++++++
1 file changed, 10 insertions(+)
--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
@@ -1221,11 +1221,21 @@ static int amd_pstate_register_driver(in
return -EINVAL;
cppc_state = mode;
+
+ ret = amd_pstate_enable(true);
+ if (ret) {
+ pr_err("failed to enable cppc during amd-pstate driver registration, return %d\n",
+ ret);
+ amd_pstate_driver_cleanup();
+ return ret;
+ }
+
ret = cpufreq_register_driver(current_pstate_driver);
if (ret) {
amd_pstate_driver_cleanup();
return ret;
}
+
return 0;
}