release 6.14.2

2025-04-11 00:38:04 +03:00
parent 12ad6316be
commit 0a221c5ce2
99 changed files with 634 additions and 2270 deletions
--- a/debian/patches/patchset-pf/amd-pstate/0024-cpufreq-amd-pstate-Stop-caching-EPP.patch
+++ b/debian/patches/patchset-pf/amd-pstate/0024-cpufreq-amd-pstate-Stop-caching-EPP.patch
@@ -0,0 +1,105 @@
+From 50fccd9d8304b992bbea9088abe4ee33786d9805 Mon Sep 17 00:00:00 2001
+From: Mario Limonciello <mario.limonciello@amd.com>
+Date: Wed, 26 Feb 2025 01:49:33 -0600
+Subject: cpufreq/amd-pstate: Stop caching EPP
+
+EPP values are cached in the cpudata structure per CPU. This is needless
+though because they are also cached in the CPPC request variable.
+
+Drop the separate cache for EPP values and always reference the CPPC
+request variable when needed.
+
+Reviewed-by: Dhananjay Ugwekar <dhananjay.ugwekar@amd.com>
+Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
+Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
+---
+ drivers/cpufreq/amd-pstate.c | 19 ++++++++++---------
+ drivers/cpufreq/amd-pstate.h |  1 -
+ 2 files changed, 10 insertions(+), 10 deletions(-)
+
+--- a/drivers/cpufreq/amd-pstate.c
+++ b/drivers/cpufreq/amd-pstate.c
+@@ -268,8 +268,6 @@ static int msr_update_perf(struct cpufre
+ 	}
+ 
+ 	WRITE_ONCE(cpudata->cppc_req_cached, value);
+-	if (epp != cpudata->epp_cached)
+-		WRITE_ONCE(cpudata->epp_cached, epp);
+ 
+ 	return 0;
+ }
+@@ -318,7 +316,6 @@ static int msr_set_epp(struct cpufreq_po
+ 	}
+ 
+ 	/* update both so that msr_update_perf() can effectively check */
+-	WRITE_ONCE(cpudata->epp_cached, epp);
+ 	WRITE_ONCE(cpudata->cppc_req_cached, value);
+ 
+ 	return ret;
+@@ -335,9 +332,12 @@ static int shmem_set_epp(struct cpufreq_
+ {
+ 	struct amd_cpudata *cpudata = policy->driver_data;
+ 	struct cppc_perf_ctrls perf_ctrls;
+	u8 epp_cached;
+ 	u64 value;
+ 	int ret;
+ 
+
+	epp_cached = FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached);
+ 	if (trace_amd_pstate_epp_perf_enabled()) {
+ 		union perf_cached perf = cpudata->perf;
+ 
+@@ -348,10 +348,10 @@ static int shmem_set_epp(struct cpufreq_
+ 					  FIELD_GET(AMD_CPPC_MAX_PERF_MASK,
+ 						    cpudata->cppc_req_cached),
+ 					  policy->boost_enabled,
+-					  epp != cpudata->epp_cached);
+					  epp != epp_cached);
+ 	}
+ 
+-	if (epp == cpudata->epp_cached)
+	if (epp == epp_cached)
+ 		return 0;
+ 
+ 	perf_ctrls.energy_perf = epp;
+@@ -360,7 +360,6 @@ static int shmem_set_epp(struct cpufreq_
+ 		pr_debug("failed to set energy perf value (%d)\n", ret);
+ 		return ret;
+ 	}
+-	WRITE_ONCE(cpudata->epp_cached, epp);
+ 
+ 	value = READ_ONCE(cpudata->cppc_req_cached);
+ 	value &= ~AMD_CPPC_EPP_PERF_MASK;
+@@ -1168,9 +1167,11 @@ static ssize_t show_energy_performance_p
+ 				struct cpufreq_policy *policy, char *buf)
+ {
+ 	struct amd_cpudata *cpudata = policy->driver_data;
+-	u8 preference;
+	u8 preference, epp;
+
+	epp = FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached);
+ 
+-	switch (cpudata->epp_cached) {
+	switch (epp) {
+ 	case AMD_CPPC_EPP_PERFORMANCE:
+ 		preference = EPP_INDEX_PERFORMANCE;
+ 		break;
+@@ -1533,7 +1534,7 @@ static int amd_pstate_epp_update_limit(s
+ 	if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE)
+ 		epp = 0;
+ 	else
+-		epp = READ_ONCE(cpudata->epp_cached);
+		epp = FIELD_GET(AMD_CPPC_EPP_PERF_MASK, cpudata->cppc_req_cached);
+ 
+ 	perf = READ_ONCE(cpudata->perf);
+ 
+--- a/drivers/cpufreq/amd-pstate.h
+++ b/drivers/cpufreq/amd-pstate.h
+@@ -102,7 +102,6 @@ struct amd_cpudata {
+ 	bool	hw_prefcore;
+ 
+ 	/* EPP feature related attributes*/
+-	u8	epp_cached;
+ 	u32	policy;
+ 	bool	suspended;
+ 	u8	epp_default;