31 lines
985 B
Diff
31 lines
985 B
Diff
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From de31d4a11e894a73ed7ef2388fb27f0bb4036de3 Mon Sep 17 00:00:00 2001
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From: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
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Date: Wed, 23 Oct 2024 10:21:08 +0000
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Subject: cpufreq/amd-pstate: Do not attempt to clear MSR_AMD_CPPC_ENABLE
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MSR_AMD_CPPC_ENABLE is a write once register, i.e. attempting to clear
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it is futile, it will not take effect. Hence, return if disable (0)
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argument is passed to the msr_cppc_enable()
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Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
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Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
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---
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drivers/cpufreq/amd-pstate.c | 6 ++++++
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1 file changed, 6 insertions(+)
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--- a/drivers/cpufreq/amd-pstate.c
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+++ b/drivers/cpufreq/amd-pstate.c
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@@ -341,6 +341,12 @@ static inline int msr_cppc_enable(bool e
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int ret, cpu;
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unsigned long logical_proc_id_mask = 0;
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+ /*
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+ * MSR_AMD_CPPC_ENABLE is write-once, once set it cannot be cleared.
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+ */
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+ if (!enable)
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+ return 0;
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+
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if (enable == cppc_enabled)
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return 0;
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