2025-02-09 19:40:34 +03:00
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From 101ba03a6474bbc52971505abf1e3ee9613f255b Mon Sep 17 00:00:00 2001
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2025-01-28 09:25:42 +03:00
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From: Rik van Riel <riel@surriel.com>
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2025-02-09 19:40:34 +03:00
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Date: Wed, 5 Feb 2025 23:43:30 -0500
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2025-01-28 09:25:42 +03:00
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Subject: x86/mm: enable AMD translation cache extensions
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With AMD TCE (translation cache extensions) only the intermediate mappings
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that cover the address range zapped by INVLPG / INVLPGB get invalidated,
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rather than all intermediate mappings getting zapped at every TLB invalidation.
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This can help reduce the TLB miss rate, by keeping more intermediate
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mappings in the cache.
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From the AMD manual:
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Translation Cache Extension (TCE) Bit. Bit 15, read/write. Setting this bit
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to 1 changes how the INVLPG, INVLPGB, and INVPCID instructions operate on
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TLB entries. When this bit is 0, these instructions remove the target PTE
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from the TLB as well as all upper-level table entries that are cached
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in the TLB, whether or not they are associated with the target PTE.
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When this bit is set, these instructions will remove the target PTE and
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only those upper-level entries that lead to the target PTE in
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the page table hierarchy, leaving unrelated upper-level entries intact.
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Signed-off-by: Rik van Riel <riel@surriel.com>
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2025-02-09 19:40:34 +03:00
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Tested-by: Manali Shukla <Manali.Shukla@amd.com>
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2025-01-28 09:25:42 +03:00
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---
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arch/x86/include/asm/msr-index.h | 2 ++
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arch/x86/kernel/cpu/amd.c | 4 ++++
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tools/arch/x86/include/asm/msr-index.h | 2 ++
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3 files changed, 8 insertions(+)
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--- a/arch/x86/include/asm/msr-index.h
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+++ b/arch/x86/include/asm/msr-index.h
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@@ -25,6 +25,7 @@
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#define _EFER_SVME 12 /* Enable virtualization */
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#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
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#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
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+#define _EFER_TCE 15 /* Enable Translation Cache Extensions */
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#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */
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#define EFER_SCE (1<<_EFER_SCE)
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@@ -34,6 +35,7 @@
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#define EFER_SVME (1<<_EFER_SVME)
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#define EFER_LMSLE (1<<_EFER_LMSLE)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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+#define EFER_TCE (1<<_EFER_TCE)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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/*
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--- a/arch/x86/kernel/cpu/amd.c
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+++ b/arch/x86/kernel/cpu/amd.c
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@@ -1071,6 +1071,10 @@ static void init_amd(struct cpuinfo_x86
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/* AMD CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
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clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
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+
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+ /* Enable Translation Cache Extension */
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+ if (cpu_feature_enabled(X86_FEATURE_TCE))
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+ msr_set_bit(MSR_EFER, _EFER_TCE);
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}
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#ifdef CONFIG_X86_32
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--- a/tools/arch/x86/include/asm/msr-index.h
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+++ b/tools/arch/x86/include/asm/msr-index.h
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@@ -25,6 +25,7 @@
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#define _EFER_SVME 12 /* Enable virtualization */
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#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
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#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
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+#define _EFER_TCE 15 /* Enable Translation Cache Extensions */
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#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */
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#define EFER_SCE (1<<_EFER_SCE)
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@@ -34,6 +35,7 @@
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#define EFER_SVME (1<<_EFER_SVME)
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#define EFER_LMSLE (1<<_EFER_LMSLE)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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+#define EFER_TCE (1<<_EFER_TCE)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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/*
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