37 lines
1.1 KiB
Diff
37 lines
1.1 KiB
Diff
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From a9b210306e861b7c2d3b8532c85e8cd54c3b322a Mon Sep 17 00:00:00 2001
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From: Mario Limonciello <mario.limonciello@amd.com>
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Date: Thu, 5 Dec 2024 16:28:39 -0600
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Subject: cpufreq/amd-pstate: Only update the cached value in msr_set_epp() on
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success
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If writing the MSR MSR_AMD_CPPC_REQ fails then the cached value in the
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amd_cpudata structure should not be updated.
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Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
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---
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drivers/cpufreq/amd-pstate.c | 10 +++++++---
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1 file changed, 7 insertions(+), 3 deletions(-)
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--- a/drivers/cpufreq/amd-pstate.c
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+++ b/drivers/cpufreq/amd-pstate.c
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@@ -308,11 +308,15 @@ static int msr_set_epp(struct amd_cpudat
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value &= ~AMD_PSTATE_EPP_PERF_MASK;
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value |= FIELD_PREP(AMD_PSTATE_EPP_PERF_MASK, epp);
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- WRITE_ONCE(cpudata->cppc_req_cached, value);
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ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
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- if (!ret)
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- cpudata->epp_cached = epp;
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+ if (ret) {
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+ pr_err("failed to set energy perf value (%d)\n", ret);
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+ return ret;
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+ }
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+
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+ cpudata->epp_cached = epp;
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+ WRITE_ONCE(cpudata->cppc_req_cached, value);
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return ret;
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}
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