83 lines
2.8 KiB
Diff
83 lines
2.8 KiB
Diff
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From 021028e977fcd835ed92a4543f7977a8aa0c1dd6 Mon Sep 17 00:00:00 2001
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From: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
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Date: Wed, 4 Dec 2024 14:48:40 +0000
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Subject: cpufreq/amd-pstate: Refactor amd_pstate_epp_reenable() and
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amd_pstate_epp_offline()
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Replace similar code chunks with amd_pstate_update_perf() and
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amd_pstate_set_epp() function calls.
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Signed-off-by: Dhananjay Ugwekar <Dhananjay.Ugwekar@amd.com>
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Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
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Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
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---
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drivers/cpufreq/amd-pstate.c | 38 +++++++-----------------------------
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1 file changed, 7 insertions(+), 31 deletions(-)
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--- a/drivers/cpufreq/amd-pstate.c
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+++ b/drivers/cpufreq/amd-pstate.c
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@@ -1660,25 +1660,17 @@ static int amd_pstate_epp_set_policy(str
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static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata)
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{
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- struct cppc_perf_ctrls perf_ctrls;
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- u64 value, max_perf;
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+ u64 max_perf;
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int ret;
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ret = amd_pstate_cppc_enable(true);
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if (ret)
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pr_err("failed to enable amd pstate during resume, return %d\n", ret);
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- value = READ_ONCE(cpudata->cppc_req_cached);
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max_perf = READ_ONCE(cpudata->highest_perf);
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- if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
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- wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
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- } else {
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- perf_ctrls.max_perf = max_perf;
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- cppc_set_perf(cpudata->cpu, &perf_ctrls);
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- perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached);
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- cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
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- }
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+ amd_pstate_update_perf(cpudata, 0, 0, max_perf, false);
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+ amd_pstate_set_epp(cpudata, cpudata->epp_cached);
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}
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static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy)
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@@ -1698,31 +1690,15 @@ static int amd_pstate_epp_cpu_online(str
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static void amd_pstate_epp_offline(struct cpufreq_policy *policy)
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{
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struct amd_cpudata *cpudata = policy->driver_data;
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- struct cppc_perf_ctrls perf_ctrls;
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int min_perf;
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- u64 value;
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min_perf = READ_ONCE(cpudata->lowest_perf);
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- value = READ_ONCE(cpudata->cppc_req_cached);
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mutex_lock(&amd_pstate_limits_lock);
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- if (cpu_feature_enabled(X86_FEATURE_CPPC)) {
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- cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN;
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- /* Set max perf same as min perf */
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- value &= ~AMD_CPPC_MAX_PERF(~0L);
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- value |= AMD_CPPC_MAX_PERF(min_perf);
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- value &= ~AMD_CPPC_MIN_PERF(~0L);
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- value |= AMD_CPPC_MIN_PERF(min_perf);
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- wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value);
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- } else {
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- perf_ctrls.desired_perf = 0;
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- perf_ctrls.min_perf = min_perf;
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- perf_ctrls.max_perf = min_perf;
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- cppc_set_perf(cpudata->cpu, &perf_ctrls);
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- perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(HWP_EPP_BALANCE_POWERSAVE);
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- cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1);
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- }
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+ amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false);
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+ amd_pstate_set_epp(cpudata, AMD_CPPC_EPP_BALANCE_POWERSAVE);
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+
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mutex_unlock(&amd_pstate_limits_lock);
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}
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