133 lines
3.8 KiB
Diff
133 lines
3.8 KiB
Diff
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From ea6b500eb38124a59e83254435340e0390117c54 Mon Sep 17 00:00:00 2001
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From: Mario Limonciello <mario.limonciello@amd.com>
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Date: Thu, 5 Dec 2024 16:28:33 -0600
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Subject: cpufreq/amd-pstate: Add trace event for EPP perf updates
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In "active" mode the most important thing for debugging whether
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an issue is hardware or software based is to look at what was the
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last thing written to the CPPC request MSR or shared memory region.
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The 'amd_pstate_epp_perf' trace event shows the values being written
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for all CPUs.
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Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
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Reviewed-by: Perry Yuan <perry.yuan@amd.com>
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Reviewed-by: Gautham R. Shenoy <gautham.shenoy@amd.com>
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---
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drivers/cpufreq/amd-pstate-trace.h | 45 ++++++++++++++++++++++++++++++
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drivers/cpufreq/amd-pstate.c | 28 +++++++++++++++++++
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2 files changed, 73 insertions(+)
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--- a/drivers/cpufreq/amd-pstate-trace.h
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+++ b/drivers/cpufreq/amd-pstate-trace.h
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@@ -88,6 +88,51 @@ TRACE_EVENT(amd_pstate_perf,
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)
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);
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+TRACE_EVENT(amd_pstate_epp_perf,
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+
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+ TP_PROTO(unsigned int cpu_id,
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+ unsigned int highest_perf,
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+ unsigned int epp,
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+ unsigned int min_perf,
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+ unsigned int max_perf,
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+ bool boost
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+ ),
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+
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+ TP_ARGS(cpu_id,
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+ highest_perf,
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+ epp,
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+ min_perf,
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+ max_perf,
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+ boost),
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+
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+ TP_STRUCT__entry(
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+ __field(unsigned int, cpu_id)
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+ __field(unsigned int, highest_perf)
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+ __field(unsigned int, epp)
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+ __field(unsigned int, min_perf)
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+ __field(unsigned int, max_perf)
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+ __field(bool, boost)
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+ ),
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+
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+ TP_fast_assign(
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+ __entry->cpu_id = cpu_id;
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+ __entry->highest_perf = highest_perf;
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+ __entry->epp = epp;
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+ __entry->min_perf = min_perf;
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+ __entry->max_perf = max_perf;
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+ __entry->boost = boost;
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+ ),
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+
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+ TP_printk("cpu%u: [%u<->%u]/%u, epp=%u, boost=%u",
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+ (unsigned int)__entry->cpu_id,
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+ (unsigned int)__entry->min_perf,
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+ (unsigned int)__entry->max_perf,
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+ (unsigned int)__entry->highest_perf,
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+ (unsigned int)__entry->epp,
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+ (bool)__entry->boost
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+ )
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+);
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+
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#endif /* _AMD_PSTATE_TRACE_H */
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/* This part must be outside protection */
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--- a/drivers/cpufreq/amd-pstate.c
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+++ b/drivers/cpufreq/amd-pstate.c
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@@ -354,6 +354,14 @@ static int amd_pstate_set_energy_pref_in
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return -EBUSY;
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}
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+ if (trace_amd_pstate_epp_perf_enabled()) {
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+ trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf,
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+ epp,
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+ AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached),
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+ AMD_CPPC_MAX_PERF(cpudata->cppc_req_cached),
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+ cpudata->boost_state);
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+ }
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+
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ret = amd_pstate_set_epp(cpudata, epp);
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return ret;
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@@ -1626,6 +1634,13 @@ static int amd_pstate_epp_update_limit(s
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WRITE_ONCE(cpudata->cppc_req_cached, value);
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+ if (trace_amd_pstate_epp_perf_enabled()) {
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+ trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf, epp,
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+ cpudata->min_limit_perf,
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+ cpudata->max_limit_perf,
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+ cpudata->boost_state);
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+ }
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+
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amd_pstate_update_perf(cpudata, cpudata->min_limit_perf, 0U,
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cpudata->max_limit_perf, false);
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@@ -1669,6 +1684,13 @@ static void amd_pstate_epp_reenable(stru
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max_perf = READ_ONCE(cpudata->highest_perf);
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+ if (trace_amd_pstate_epp_perf_enabled()) {
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+ trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf,
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+ cpudata->epp_cached,
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+ AMD_CPPC_MIN_PERF(cpudata->cppc_req_cached),
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+ max_perf, cpudata->boost_state);
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+ }
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+
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amd_pstate_update_perf(cpudata, 0, 0, max_perf, false);
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amd_pstate_set_epp(cpudata, cpudata->epp_cached);
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}
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@@ -1697,6 +1719,12 @@ static int amd_pstate_epp_cpu_offline(st
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mutex_lock(&amd_pstate_limits_lock);
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+ if (trace_amd_pstate_epp_perf_enabled()) {
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+ trace_amd_pstate_epp_perf(cpudata->cpu, cpudata->highest_perf,
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+ AMD_CPPC_EPP_BALANCE_POWERSAVE,
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+ min_perf, min_perf, cpudata->boost_state);
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+ }
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+
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amd_pstate_update_perf(cpudata, min_perf, 0, min_perf, false);
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amd_pstate_set_epp(cpudata, AMD_CPPC_EPP_BALANCE_POWERSAVE);
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